SLLU326A May   2022  – June 2022 TLIN1431-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Features
    2. 1.2 Description
  4. 2EVM Setup and Features
    1. 2.1  Startup Mode Configurations
      1. 2.1.1 Pin and SPI Modes
      2. 2.1.2 Wake Request (WKRQ) vs. Inhibit Output (INH)
    2. 2.2  Commander and Responder Configurations
    3. 2.3  Local Wake-Up
    4. 2.4  Channel Expansion
    5. 2.5  VBAT Voltage Divider
    6. 2.6  Reset Input
    7. 2.7  Logic-Level LIMP and WAKE Signals
    8. 2.8  High-Voltage Signal Monitoring
    9. 2.9  TXD and RXD
    10. 2.10 VCC Load Testing
    11. 2.11 SPI Interface
  5. 3Jumpers, Headers, Connectors, Test Points, and Switches
  6. 4Bill of Materials
  7. 5Schematic

2.1.1 Pin and SPI Modes

Two modes of operation are available on the TLIN1431-Q1: pin mode and SPI mode. The mode of the device is determined by the state of pin 7 (PIN/nCS) upon power-up. If pin 7 is pulled low or connected to GND at startup, the device operates in pin mode, with no SPI interface. If pin 7 is left floating or pulled high at startup, then the device operates in SPI mode, where the SPI interface is enabled and the user can access the internal registers of the device.

Additionally, the TLIN14315-Q1 is capable of VIO less operation as determined by the biasing of this PIN/nCS pin. If it is left floating, the device operates using 3.3 V SPI communication. If it is pulled high to 5 V, then it operates using 5 V SPI communication.

Figure 2-1 PIN/nCS Configuration

Note the TLIN14313-Q1, which includes a 3.3 V LDO, does not include VIOless operation and is only capable of 3.3 V SPI communication.

J5 allows for easy biasing of the PIN/nCS pin to either a pull-down resistor for pin mode or floating/pull-up for VIOless SPI mode operation.

The TLIN1431-Q1 device has alternate pin designations and functions depending on the power-up mode chosen. The designations are shown in Table 2-1, and the functions of each pin are described in the TLIN1431-Q1 data sheet.

Table 2-1 Pinout in Pin Mode vs. Pinout in SPI Mode
PinPin modeSPI mode
4WDT – Programmable watchdog window set inputCLK – SPI clock input
5nWDR – Watchdog failure output triggerSDO – SPI serial data output
6WDI – Watchdog timer edge-triggered inputSDI – SPI serial data input
7PIN – Input that sets the device to pin modenCS – SPI chip select
8EN – Device mode change inputnINT – Device interrupt output
9HSSC – High-side switch control inputFSO – Function output

The user can start up the TLIN1431-Q1 into pin mode by connecting a shunt between pins “PIN/nCS” and “GND_PD” of J5, which applies a pull-down to GND to pin 7. Leaving all pins of J5 floating results in the TLIN1431-Q1 operating in SPI mode, and the TLIN14315-Q1 operates with 3.3 V SPI. Connect a shunt between pins “PIN/nCS” and “VCC_PU” of J5 to apply a pull-up to VCC, resulting in 5 V SPI operation for the TLIN14315-Q1.