SLLU326A May   2022  – June 2022 TLIN1431-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Features
    2. 1.2 Description
  4. 2EVM Setup and Features
    1. 2.1  Startup Mode Configurations
      1. 2.1.1 Pin and SPI Modes
      2. 2.1.2 Wake Request (WKRQ) vs. Inhibit Output (INH)
    2. 2.2  Commander and Responder Configurations
    3. 2.3  Local Wake-Up
    4. 2.4  Channel Expansion
    5. 2.5  VBAT Voltage Divider
    6. 2.6  Reset Input
    7. 2.7  Logic-Level LIMP and WAKE Signals
    8. 2.8  High-Voltage Signal Monitoring
    9. 2.9  TXD and RXD
    10. 2.10 VCC Load Testing
    11. 2.11 SPI Interface
  5. 3Jumpers, Headers, Connectors, Test Points, and Switches
  6. 4Bill of Materials
  7. 5Schematic

2.10 VCC Load Testing

The LDO output (VCC) is accessible using TP4 or via pin 1 of J4. The user can apply a load to these pins to test the stability and performance of the LDO on the TLIN1431-Q1.