SLLU326A May   2022  – June 2022 TLIN1431-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Features
    2. 1.2 Description
  4. 2EVM Setup and Features
    1. 2.1  Startup Mode Configurations
      1. 2.1.1 Pin and SPI Modes
      2. 2.1.2 Wake Request (WKRQ) vs. Inhibit Output (INH)
    2. 2.2  Commander and Responder Configurations
    3. 2.3  Local Wake-Up
    4. 2.4  Channel Expansion
    5. 2.5  VBAT Voltage Divider
    6. 2.6  Reset Input
    7. 2.7  Logic-Level LIMP and WAKE Signals
    8. 2.8  High-Voltage Signal Monitoring
    9. 2.9  TXD and RXD
    10. 2.10 VCC Load Testing
    11. 2.11 SPI Interface
  5. 3Jumpers, Headers, Connectors, Test Points, and Switches
  6. 4Bill of Materials
  7. 5Schematic

2.11 SPI Interface

When operating in SPI mode, pins 4-7 of the TLIN1431-Q1 become the SPI interface for the device. Specifically, “WDT/CLK” is the SPI clock input, “nWDR/SDO” is the SPI serial data output, “WDI/SDI” is the SPI serial data input, and “PIN/nCS” is the SPI active-low chip select.

The four SPI interface pins are accessible via J4, pins 12, 14, 16, and 18. These four signals are vertically separated from the rest of the logic signals on J4. Per the silkscreen legend on the board, these four signals are on the leftmost column of J4, while the remaining signals on this header are located on the rightmost column.

These four SPI signals can be connected to a micro controller or similar processor to control the TLIN1431-Q1 via SPI. Note that the device must start up with PIN/nCS (pin 7) floating or pulled high to interface via SPI mode.