SLOA011B January   2018  – July 2021 LF347 , LF353 , LM348 , MC1458 , TL022 , TL061 , TL062 , TL071 , TL072 , UA741

 

  1. 1Introduction
    1. 1.1 Amplifier Basics
    2. 1.2 Ideal Op Amp Model
  2. 2Non-Inverting Amplifier
    1. 2.1 Closed Loop Concepts and Simplifications
  3. 3Inverting Amplifier
    1. 3.1 Closed Loop Concepts and Simplifications
  4. 4Simplified Op Amp Circuit Diagram
    1. 4.1 Input Stage
    2. 4.2 Second Stage
    3. 4.3 Output Stage
  5. 5Op Amp Specifications
    1. 5.1  Absolute Maximum Ratings and Recommended Operating Condition
    2. 5.2  Input Offset Voltage
    3. 5.3  Input Current
    4. 5.4  Input Common Mode Voltage Range
    5. 5.5  Differential Input Voltage Range
    6. 5.6  Maximum Output Voltage Swing
    7. 5.7  Large Signal Differential Voltage Amplification
    8. 5.8  Input Parasitic Elements
      1. 5.8.1 Input Capacitance
      2. 5.8.2 Input Resistance
    9. 5.9  Output Impedance
    10. 5.10 Common-Mode Rejection Ratio
    11. 5.11 Supply Voltage Rejection Ratio
    12. 5.12 Supply Current
    13. 5.13 Slew Rate at Unity Gain
    14. 5.14 Equivalent Input Noise
    15. 5.15 Total Harmonic Distortion Plus Noise
    16. 5.16 Unity-Gain Bandwidth and Phase Margin
    17. 5.17 Settling Time
  6. 6References
  7. 7Glossary
  8. 8Revision History

5.17 Settling Time

It takes a finite time for a signal to propagate through the internal circuitry of an op amp. Therefore, it takes a certain period of time for the output to react to a step change in the input. Also the output normally overshoots the target value, experiences damped oscillation, and settles to a final value. Settling time, ts, is the time required for the output voltage to settle to within a specified percentage of the final value given a step input. Figure 5-13 shows this graphically.

GUID-2BE5D37D-27E4-4F6E-B034-D58DC88E7A33-low.gifFigure 5-13 Settling Time

Settling time is a design issue in data acquisition circuits when signals are changing rapidly. An example is when using an op amp following a multiplexer to buffer the input to an analog to digital converter. Step changes can occur at the input to the op amp when the multiplexer changes channels. The output of the op amp must settle to within a certain tolerance before the analog to digital converter samples the signal.