DC Parameters: Input Offset Voltage (VOS)

Abstract

The input offset voltage (V_OS) is a common DC parameter in operational amplifier (op amp) specifications. This report aims to familiarize the engineer with the basics and modern aspects of V_OS by providing a definition and a detailed explanation of causes of V_OS for BJT, JFET, and CMOS devices. The article centers around measurement techniques, data sheet specifications, the effect of V_OS on circuit design, and the trim methods to correct it.

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1 Introduction

Op amps find extensive use in a wide variety of circuits, and their appropriate specification for a particular application requires knowledge of relevant data sheet parameters. Data sheet specifications are divided into two general categories: DC parameters and AC parameters. The DC parameters represent internal errors that occur as a result of mismatches between devices and components inside the op amp. These errors are always present from the time the power is turned on (for example, before, during, and after any input signal is applied), and they determine how precisely the output matches the ideal op amp model. Thus, the precision of the op amp is determined by the magnitude of the DC errors.

The objective of this report is to provide the information necessary for the designer to understand each parameter: what it is; what causes it; and how it is measured, trimmed, and specified.

Figure 1-1 presents an ideal op amp model together with a table of ideal parameters (see Understanding Basic Analog – Ideal Op Amps for more information on the ideal op amp). The general assumptions listed in the table simplify design analysis and provide a good first order approximation that is reasonable when the op amp limits are not being pushed. Most applications, however, use the op amp to the fullest extent for one or more parameters and require more detailed analysis. It is then that the non ideal, or real, op amp model must be used. Figure 1-2 shows this non ideal op amp model and uses the OPAx991 as an example for the op amp typical parameter values.

Figure 1-1 Ideal Op Amp Model and Model Parameters

Figure 1-2 Non ideal Op Amp Model

2 Input Offset Voltage Defined

The input offset voltage (V_OS) is defined as the voltage that must be applied between the two input terminals of the op amp to obtain zero volts at the output. V_OS is symbolically represented by a voltage source that is in series with either the positive or negative input terminal (it is mathematically equivalent either way). V_OS is considered to be a DC error and is present from the moment that power is applied until it is turned off, with or without an input signal. It occurs during the biasing of the op amp and its effect can only be reduced, not eliminated.

It can be either negative or positive in polarity and can vary from device to device (die to die) of the same wafer lot. Figure 2-1 shows the distribution of V_OS measured in one wafer lot of the OPA2991 op amp as an example of the variance that V_OS can have.

Figure 2-1 Distribution of V_OS for the OPA2991

3 Cause of V_OS

The cause of V_OS is well known: it is mostly due to the inherent mismatch of the input transistors and components during fabrication of the silicon die, but stresses placed on the die during the packaging process have a minor contribution. These effects collectively produce a mismatch of the bias currents that flow through the input circuit, and primarily the input devices, resulting in a voltage differential at the input terminals of the op amp. V_OS has been reduced with modern manufacturing processes through increased matching and improved package materials and assembly.

The input stage of most op amps consists of a differential pair amplifier. A simplified version is shown in Figure 3-1, where Q₁ (+ or non-inverting input terminal) and Q₂ (– or inverting input terminal) can be BJT, FET, or MOS transistors. The input terminals of the op amp are the bases (BJT) or gates (FET, MOS) of these transistors. The current source biases the transistors, and ideally each leg of the circuit is balanced so that one half of the current flows through each transistor ( $I_{Q 1} = I_{Q 2} = \frac{I_{REF}}{2}$ ) and the inverting and non-inverting inputs are at the same potential. Mismatches in R, Q₁, and Q₂ unbalance this current. The base (gate) voltages of the transistors then become unequal, creating the small differential voltage V_OS.

Figure 3-1 Simplified Differential Pair Amplifier. Q1 and Q2 are BJT, FET, or MOS

When the op amp is open-loop, this small differential voltage is multiplied by the open-loop gain of the amplifier (A_OL or ɑ). At the very least, the output dynamic range will be greatly reduced. Normally, however, the output of the op amp is driven to one of the power supply rails, saturating the device. When the op amp is operated closed-loop, the differential voltage is multiplied by the non-inverting closed-loop gain of the op amp, which is set by the circuit designer.