SLOA059B October   2022  – March 2023 OPA2991 , TLC2654 , TLC4502 , TLE2021 , TLV2721

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Input Offset Voltage Defined
  5. 3Cause of VOS
  6. 4VOS and Temperature Drift in the Major Device Types
    1. 4.1 Bipolar
    2. 4.2 JFET
    3. 4.3 CMOS
  7. 5Manufacturer Measurement, Trim, and Specification of VOS
    1. 5.1 Measurement
    2. 5.2 Trim
    3. 5.3 Specifications
  8. 6Impact of VOS on Circuit Design and Methods of Correction
    1. 6.1 AC Coupling
    2. 6.2 DC Feedback
    3. 6.3 Internal Calibration
  9. 7Summary
  10. 8References
  11. 9Revision History

2 Input Offset Voltage Defined

The input offset voltage (VOS) is defined as the voltage that must be applied between the two input terminals of the op amp to obtain zero volts at the output. VOS is symbolically represented by a voltage source that is in series with either the positive or negative input terminal (it is mathematically equivalent either way). VOS is considered to be a DC error and is present from the moment that power is applied until it is turned off, with or without an input signal. It occurs during the biasing of the op amp and its effect can only be reduced, not eliminated.

It can be either negative or positive in polarity and can vary from device to device (die to die) of the same wafer lot. Figure 2-1 shows the distribution of VOS measured in one wafer lot of the OPA2991 op amp as an example of the variance that VOS can have.

GUID-20220223-SS0I-P5FS-V8BD-68FZ5HKQ98M4-low.gifFigure 2-1 Distribution of VOS for the OPA2991