3 Cause of V_OS

The cause of V_OS is well known: it is mostly due to the inherent mismatch of the input transistors and components during fabrication of the silicon die, but stresses placed on the die during the packaging process have a minor contribution. These effects collectively produce a mismatch of the bias currents that flow through the input circuit, and primarily the input devices, resulting in a voltage differential at the input terminals of the op amp. V_OS has been reduced with modern manufacturing processes through increased matching and improved package materials and assembly.

The input stage of most op amps consists of a differential pair amplifier. A simplified version is shown in Figure 3-1, where Q₁ (+ or non-inverting input terminal) and Q₂ (– or inverting input terminal) can be BJT, FET, or MOS transistors. The input terminals of the op amp are the bases (BJT) or gates (FET, MOS) of these transistors. The current source biases the transistors, and ideally each leg of the circuit is balanced so that one half of the current flows through each transistor ( ${\mathrm{I}}_{\mathrm{Q}1}={\mathrm{I}}_{\mathrm{Q}2}=\frac{{\mathrm{I}}_{\mathrm{REF}}}{2}$ ) and the inverting and non-inverting inputs are at the same potential. Mismatches in R, Q₁, and Q₂ unbalance this current. The base (gate) voltages of the transistors then become unequal, creating the small differential voltage V_OS.

Figure 3-1 Simplified Differential Pair Amplifier. Q1 and Q2 are BJT, FET, or MOS

When the op amp is open-loop, this small differential voltage is multiplied by the open-loop gain of the amplifier (A_OL or ɑ). At the very least, the output dynamic range will be greatly reduced. Normally, however, the output of the op amp is driven to one of the power supply rails, saturating the device. When the op amp is operated closed-loop, the differential voltage is multiplied by the non-inverting closed-loop gain of the op amp, which is set by the circuit designer.