SLOA140B April   2009  – November 2018 TRF7960 , TRF7960A , TRF7961 , TRF7962A , TRF7963A

 

  1.   Using the SPI Interface With TRF7960
    1.     Trademarks
    2. 1 TRF7960 - SPI With SS* Mode Errata
      1. 1.1 SCLK Polarity Switch
      2. 1.2 IRQ Status Register Read
      3. 1.3 Direct Command Processing
      4. 1.4 Initialization of Derivative Registers
      5. 1.5 Transmitting One Byte Through the FIFO
      6. 1.6 Extra Dummy Bytes on RX
      7. 1.7 Timing Conditions for MOSI With Respect to S_CLK
  2.   Revision History

1.7 Timing Conditions for MOSI With Respect to S_CLK

When in SPI mode, MOSI should be able to rise or fall independent of S_CLK as long as SPI timing requirements are met. However, while in SPI mode, if MOSI has a falling edge before the end of a high period of S_CLK, then the device treats it as a parallel mode stop condition and does not register the data.

This behavior occurs only when S_CLK and MOSI are high and the state of MOSI changes from logic high to logic low before the state of S_CLK change from logic high to logic low (see Figure 8).

parallel-mode-stop-condition.gifFigure 8. Parallel Mode Stop Condition

In use cases where SPI is not naturally synchronized, the workaround is to add software guards to prevent MOSI from changing state before S_CLK.