SLOA140B April   2009  – November 2018 TRF7960 , TRF7960A , TRF7961 , TRF7962A , TRF7963A

 

  1.   Using the SPI Interface With TRF7960
    1.     Trademarks
    2. 1 TRF7960 - SPI With SS* Mode Errata
      1. 1.1 SCLK Polarity Switch
      2. 1.2 IRQ Status Register Read
      3. 1.3 Direct Command Processing
      4. 1.4 Initialization of Derivative Registers
      5. 1.5 Transmitting One Byte Through the FIFO
      6. 1.6 Extra Dummy Bytes on RX
      7. 1.7 Timing Conditions for MOSI With Respect to S_CLK
  2.   Revision History

1 TRF7960 - SPI With SS* Mode Errata

It is important to note that there are some nonstandard conditions when the TRF7960 is operated in the SPI mode. Table 1 lists these conditions and the software patches to work around them.

Table 1. Nonstandard Conditions

Condition Software Fix
SCLK clock polarity switch needed when read operation (single or continuous) is executed. Firmware fix to switch clock polarity between writes and reads (see Section 1.1).
IRQ Status register is not automatically cleared after reading. Dummy read is needed to clear the contents of IRQ status register and hence drive the IRQ pin low (see Section 1.2).
All stand-alone (single-byte) direct commands need additional clock cycle to work. An example is the slot markers (EOF) for ISO 15693 do not work in SPI mode. All direct command functions need to have this additional SW fix.
Direct commands like “Transmit Next Slot” needs to have additional SCLK cycle before SS* goes high (see Section 1.3).
Some of the registers (RX wait time, RX no response wait time) do not take default values when the appropriate protocol is chosen in the ISO control register. Manually program these defaults again in the initialization routine (see Section 1.4).
Transmitting one byte through the FIFO. Split the command (See Section 1.5).

The serial interface is in reset while the SS* signal is high. Serial Data-In (MOSI) changes on the falling edge, and are validated in the reader on the rising edge (see Figure 1). Communication is terminated when SS* signal goes inactive (high). All words must be 8 bits long with the MSB transmitted first.

write_loa140.gifFigure 1. Serial - SPI Interface Communication (Write Mode)