SLOA343 August   2024 TPS543820 , TPS543A22 , TPSM843620 , TPSM843A22

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Layout Techniques to Reduce EMI
    1. 2.1 Placement of Passive Components
    2. 2.2 Ground Flooding
    3. 2.3 Minimize Number of Antennas
    4. 2.4 Via Stitching
    5. 2.5 Additional Steps to Minimize Impedance or Noise
  6. 3Designing for EMI-Optimized Layout
  7. 4Test Results for Radiated Interference
  8. 5EMI Filtering
  9. 6Summary
  10. 7References

Via Stitching

The via stitching technique consists of using via connections between outer ground layers. By creating these evenly spaced vias around the circuit, a ground loop connection shown in Figure 2-1 is avoided and you end up with Figure 2-2. This direct connection to ground further lowers the impedance and parasitic in the PCB.

 Ground Loop
                        ConnectionFigure 2-1 Ground Loop Connection
 Avoided Ground Loop
                        Connection With ViasFigure 2-2 Avoided Ground Loop Connection With Vias