SLOS488 Data sheet

SLOS488F November 2006 – March 2015 TPA6130A2

PRODUCTION DATA.

8 Detailed Description

8.1 Overview

Headphone channels are independently enabled and muted. The I²C interface controls channel gain, device modes, and charge pump activation. The charge pump generates a negative supply voltage for the output amplifiers. This allows a 0 V bias at the outputs, eliminating the need for bulky output capacitors. The thermal block detects faults and shuts down the device before damage occurs. The I²C register records thermal fault conditions. The current limit block prevents the output current from getting high enough to damage the device. The De-Pop block eliminates audible pops during power-up, power-down, and amplifier enable and disable events.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Headphone Amplifiers

Two different headphone amplifier applications are available that allow for the removal of the output dc blocking capacitors. The Capless amplifier architecture is implemented in the same manner as the conventional amplifier with the exception of the headphone jack shield pin. This amplifier provides a reference voltage, which is connected to the headphone jack shield pin. This is the voltage on which the audio output signals are centered. This voltage reference is half of the amplifier power supply to allow symmetrical swing of the output voltages. Do not connect the shield to any GND reference or large currents will result. The scenario can happen if, for example, an accessory other than a floating GND headphone is plugged into the headphone connector. See the second block diagram and waveform in Figure 34.

Figure 34. Amplifier Applications

The DirectPath™ amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. The DirectPath™ amplifier requires no output dc blocking capacitors, and does not place any voltage on the sleeve. The bottom block diagram and waveform of Figure 34 illustrate the ground-referenced headphone architecture. This is the architecture of the TPA6130A2.

8.4 Device Functional Modes

The TPA6130A2 supports numerous modes of operation.

8.4.1 Hardware Shutdown

Hardware shutdown occurs when the SD pin is set to logic 0. The device is completely shutdown in this mode, drawing minimal current. This mode overrides all other modes. All information programmed into the registers is lost. When the device starts up again, the registers go back to their default state.

8.4.2 Software Shutdown

Software shutdown is set by placing a logic 1 in register 1, bit 0. That is the SWS bit. The software shutdown places the device in a low power state, although the current draw is higher than that of hardware shutdown (see the Electrical Characteristics Table for values). Engaging software shutdown turns off the charge pump and disables the outputs. The device is awakened by placing a logic 0 in the SWS bit.

Note that when the device is in SWS mode, register 1, bits 7 and 6 will be cleared to reflect the disabled state of the amplifier. All other registers maintain their values. Re-enable the amplifier by placing a logic 0 in the SWS bit. It is necessary to reset the entire register because a full word must be used when writing just one bit.

8.4.3 Charge Pump Enabled, HP Amplifiers Disabled

The output amplifiers of the TPA6130A2 are enabled by placing a logic 1 in register 1, bits 6 and 7. Place a logic 0 in register 1, bits 6 and 7 to disable the output amplifiers. The left and right outputs can be enabled and disabled individually. When the output amplifiers are disabled, the charge-pump remains on.

8.4.4 Hi-Z State

HiZ is enabled by placing a logic 1 in register 3, bits 0 and 1. Place a logic 0 in register 3, bits 0 and 1 to disable the HiZ state of the outputs. The left and right outputs can be placed into a HiZ state individually.

The HiZ state puts the outputs into a state of high impedance. Use this configuration when the outputs of the TPA6130A2 share traces with other devices whose outputs may be active.

Note that to use the HiZ mode, the TPA6130A2 MUST be active (not in SWS or hardware shutdown). Furthermore, the output amplifiers must NOT be enabled.

8.4.5 Stereo Headphone Drive

The device is in this mode when the MODE bits in register 1 are 00 and both headphone enable bits are enabled. The two amplifier channels operate independently. This mode is appropriate for stereo playback.

8.4.6 Dual Mono Headphone Drive

The device is in this mode when the MODE bits in register 1 are 01 and both headphone enable bits are enabled. The left channel is the active input. It is amplified and distributed to both the left and right headphone outputs.

8.4.7 Bridge-Tied Load Receiver Drive

The device is in this mode when the MODE bits in register 1 are 10 and both headphone enable bits are enabled. In this mode, the device will take the left channel input and drive a single load connected between HPLEFT and HPRIGHT in a bridge-tied fashion. The minimum load for bridge-tied mode is the same as for stereo mode (see table entitled "Absolute Maximum Ratings").

8.4.8 Default Mode

The TPA6130A2 starts up with the following conditions:

SWS = Off, CHARGE PUMP = On
HP ENABLES = Off
HiZ = Off
MODE = Stereo
HP MUTES = On, VOLUME = -59.5 dB,

8.4.9 Volume Control

The TPA6130A2 volume control is set through the I²C interface. The six volume control register bits are decoded to 64 volume settings that employ an audio taper. See Table 2 for the gain table. The values listed in this table are typical. Each gain step has a different input impedance. See Figure 33.

Table 2. Audio Taper Gain Values

Gain Control Word (Binary) Mute [7:6], V[5:0]	Nominal Gain (dB)	Nominal Gain (V/V)	Gain Control Word (Binary) Mute [7:6], V[5:0]	Nominal Gain (dB)	Nominal Gain (V/V)
11XXXXXX	–100	0.00001	00100000	–10.9	0.283
00000000	–59.5	0.001	00100001	–10.3	0.305
00000001	–53.5	0.002	00100010	–9.7	0.329
00000010	–50.0	0.003	00100011	–9.0	0.353
00000011	–47.5	0.004	00100100	–8.5	0.379
00000100	–45.5	0.005	00100101	–7.8	0.405
00000101	–43.9	0.007	00100110	–7.2	0.433
00000110	–41.4	0.009	00100111	–6.7	0.462
00000111	–39.5	0.012	00101000	–6.1	0.493
00001000	–36.5	0.015	00101001	–5.6	0.524
00001001	–35.3	0.018	00101010	–5.1	0.557
00001010	–33.3	0.022	00101011	–4.5	0.591
00001011	–31.7	0.026	00101100	–4.1	0.627
00001100	–30.4	0.031	00101101	–3.5	0.664
00001101	–28.6	0.037	00101110	–3.1	0.702
00001110	–27.1	0.043	00101111	–2.6	0.742
00001111	–26.3	0.050	00110000	–2.1	0.783
00010000	–24.7	0.057	00110001	–1.7	0.825
00010001	–23.7	0.065	00110010	–1.2	0.870
00010010	–22.5	0.074	00110011	–0.8	0.915
00010011	–21.7	0.084	00110100	–0.3	0.962
00010100	–20.5	0.093	00110101	0.1	1.010
00010101	–19.6	0.104	00110110	0.5	1.061
00010110	–18.8	0.116	00110111	0.9	1.112
00010111	–17.8	0.129	00111000	1.4	1.165
00011000	–17.0	0.142	00111001	1.7	1.220
00011001	–16.2	0.156	00111010	2.1	1.277
00011010	–15.2	0.172	00111011	2.5	1.335
00011011	–14.5	0.188	00111100	2.9	1.395
00011100	–13.7	0.205	00111101	3.3	1.456
00011101	–13.0	0.223	00111110	3.6	1.520
00011110	–12.3	0.242	00111111	4.0	1.585
00011111	–11.6	0.262

8.5 Programming

8.5.1 General I²C Operation

The I²C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 35. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then wait for an acknowledge condition. The TPA6130A2 holds SDA low during acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection.

An external pull-up resistor must be used for the SDA and SCL signals to set the HIGH level for the bus. When the bus level is 5 V, pull-up resistors between 1 kΩ and 2 kΩ in value must be used.

Figure 35. Typical I²C Sequence

There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 35.

8.5.2 Single-and Multiple-Byte Transfers

The serial control interface supports both single-byte and multi-byte read/write operations for all registers.

During multiple-byte read operations, the TPA6130A2 responds with data, a byte at a time, starting at the register assigned, as long as the master device continues to respond with acknowledges.

The TPA6130A2 supports sequential I²C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I²C write transaction has taken place. For I²C sequential write transactions, the register issued then serves as the starting point, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines to how many registers are written.

8.5.3 Single-Byte Write

As shown in Figure 36, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I²C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I²C device address and the read/write bit, the TPA6130A2 responds with an acknowledge bit. Next, the master transmits the register byte corresponding to the TPA6130A2 internal memory address being accessed. After receiving the register byte, the TPA6130A2 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TPA6130A2 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer.

Figure 36. Single-Byte Write Transfer

8.5.4 Multiple-Byte Write and Incremental Multiple-Byte Write

A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the TPA6130A2 as shown in Figure 37. After receiving each data byte, the TPA6130A2 responds with an acknowledge bit.

Figure 37. Multiple-Byte Write Transfer

8.5.5 Single-Byte Read

As shown in Figure 38, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I²C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory address to be read. As a result, the read/write bit is set to a 0.

After receiving the TPA6130A2 address and the read/write bit, the TPA6130A2 responds with an acknowledge bit. The master then sends the internal memory address byte, after which the TPA6130A2 issues an acknowledge bit. The master device transmits another start condition followed by the TPA6130A2 address and the read/write bit again. This time the read/write bit is set to 1, indicating a read transfer. Next, the TPA6130A2 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.

Figure 38. Single-Byte Read Transfer

8.5.6 Multiple-Byte Read

A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TPA6130A2 to the master device as shown in Figure 39. With the exception of the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

Figure 39. Multiple-Byte Read Transfer

8.6 Register Maps

Table 3. Register Map

Register	Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
1	HP_EN_L	HP_EN_R	Mode[1]	Mode[0]	Reserved	Reserved	Thermal	SWS
2	Mute_L	Mute_R	Volume[5]	Volume[4]	Volume[3]	Volume[2]	Volume[1]	Volume[0]
3	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	HiZ_L	HiZ_R
4	Reserved	Reserved	RFT	RFT	Version[3]	Version[2]	Version[1]	Version[0]
5	RFT	RFT	RFT	RFT	RFT	RFT	RFT	RFT
6	RFT	RFT	RFT	RFT	RFT	RFT	RFT	RFT
7	RFT	RFT	RFT	RFT	RFT	RFT	RFT	RFT
8	RFT	RFT	RFT	RFT	RFT	RFT	RFT	RFT

Bits labeled "Reserved" are reserved for future enhancements. They may not be written to. When read, they will show a "0" value.

Bits labeled "RFT" are reserved for TI testing. Under no circumstances must any data be written to these registers. Writing to these bits may change the function of the device, or cause complete failure. If read, these bits may assume any value.