SLOS650F August   2009  – June 2016 TPA3113D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics, VCC = 24 V
    6. 6.6 DC Electrical Characteristics, VCC = 12 V
    7. 6.7 AC Electrical Characteristics, VCC = 24 V
    8. 6.8 AC Electrical Characteristics, VCC = 12 V
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Gain Setting Through GAIN0 and GAIN1 Inputs
      2. 7.3.2 SD Operation
      3. 7.3.3 PLIMIT
      4. 7.3.4 GVDD Supply
      5. 7.3.5 DC Detect
      6. 7.3.6 PBTL Select
      7. 7.3.7 Short-Circuit Protection and Automatic Recovery Feature
      8. 7.3.8 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 TPA3113D2 Modulation Scheme
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Class-D Amplifier With BTL Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Ferrite Bead Filter Considerations
          2. 8.2.1.2.2 Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme
          3. 8.2.1.2.3 When to Use an Output Filter for EMI Suppression
          4. 8.2.1.2.4 Input Resistance
          5. 8.2.1.2.5 Input Capacitor, CI
          6. 8.2.1.2.6 BSN and BSP Capacitors
          7. 8.2.1.2.7 Differential Inputs
          8. 8.2.1.2.8 Using LOW-ESR Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Stereo Class-D Amplifier With BTL Output
      3. 8.2.3 Stereo Class-D Amplifier With PBTL Output
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Decoupling, CS
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Material Recommendation
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7 Detailed Description

7.1 Overview

To facilitate system design, the TPA3113D2 needs only a single power supply between 8 V and 26 V for operation. An internal voltage regulator provides suitable voltage levels for the gate driver, digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, that is, the high-side gate drive, is accommodated by built-in bootstrap circuitry with integrated bootstrap diodes requiring only an external capacitor for each half-bridge. The audio signal path, including the gate drive and output stage is designed as identical, independent full-bridges. Pay special attention to placing all decoupling capacitors as close to their associated pins as possible. In general, the physical loop with the power supply pins, decoupling capacitors and GND return path to the device pins must be kept as short as possible and with as little area as possible to minimize induction (see reference board documentation for additional information).

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BSXX) to the power-stage output pin (OUTXX). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD) and the bootstrap pins. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 310 kHz, it is recommended to use ceramic capacitors with at least 220-nF capacitance, size 0603 or 0805, for the bootstrap supply. These capacitors ensure sufficient energy storage, even during clipped low frequency audio signals, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of its ON cycle. Pay special attention to the power-stage power supply; this includes component selection, PCB placement, and routing. For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVCC pin is decoupled with ceramic capacitors placed as close as possible to each supply pin. TI recommends following the PCB layout of the TPA3113D2 reference design. For additional information on recommended power supply and required components, see the application diagrams in this data sheet. The PVCC power supply must have low output impedance and low noise. The power-supply ramp and SD release sequence is not critical for device reliability as facilitated by the internal power-on-reset circuit, but TI recommends releasing SD after the power supply is settled for minimum turnon audible artifacts.

7.2 Functional Block Diagram

TPA3113D2 int_bd_los528.gif

7.3 Feature Description

7.3.1 Gain Setting Through GAIN0 and GAIN1 Inputs

The gain of the TPA3113D2 is set by two input terminals, GAIN0 and GAIN1. The voltage slew rate of these gain terminals, along with terminals 1 and 14, must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-kΩ resistor in series with the terminals.

The gains listed in Table 1 are realized by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.

For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 7.2 kΩ, which is the absolute minimum input impedance of the TPA3113D2. At the lower gain settings, the input impedance could increase as high as 72 kΩ.

Table 1. Gain Setting

GAIN1 GAIN0 AMPLIFIER GAIN (dB) INPUT IMPEDANCE (kΩ)
TYP TYP
0 0 20 60
0 1 26 30
1 0 32 15
1 1 36 9

7.3.2 SD Operation

The TPA3113D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of non-use for power conservation. The SD input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SD low causes the outputs to mute and the amplifier to enter a low-current state. Never leave SD unconnected, because amplifier operation would be unpredictable.

For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power supply voltage.

7.3.3 PLIMIT

The voltage at pin 10 can used to limit the power to levels below that which is possible based on the supply rail. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also be used if tighter tolerance is required. Also add a 1-μF capacitor from pin 10 to ground.

TPA3113D2 pwr_lim_los650_v2.gif Figure 29. PLIMIT Circuit Operation

The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to fixed maximum value. This limit can be thought of as a virtual voltage rail which is lower than the supply connected to PVCC. This virtual rail is 4 times the voltage at the PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance.

Equation 1. TPA3113D2 q_plimit_los528.gif

where

  • RS is the total series resistance including RDS(on), and any resistance in the output filter.
  • RL is the load resistance.
  • VP is the peak amplitude of the output possible within the supply rail.
    • VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP
    • POUT (10%THD) = 1.25 × POUT (unclipped)

Table 2. PLIMIT Typical Operation

TEST CONDITIONS PLIMIT VOLTAGE OUTPUT POWER (W) OUTPUT VOLTAGE AMPLITUDE (VP-P)
PVCC = 24 V, Vin = 1 Vrms, RL = 8 Ω,
Gain = 26 dB		 1.62 5 14
PVCC = 24 V, Vin = 1 Vrms, RL = 8 Ω,
Gain = 20 dB		 1.86 5 14.8
PVCC = 12 V, Vin = 1 Vrms, RL = 8 Ω,
Gain = 20 dB		 1.76 5 15

7.3.4 GVDD Supply

The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply the PLIMIT voltage divider circuit. Add a 1-μF capacitor to ground at this pin.

7.3.5 DC Detect

TPA3113D2 has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed-circuit board at the inputs. A DC detect fault is reported on the FAULT pin as a low state. The DC Detect fault also causes the amplifier to shutdown by changing the state of the outputs to Hi-Z. To clear the DC Detect it is necessary to cycle the PVCC supply. Cycling S D does NOT clear a DC detect fault.

A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 14% (for example, +57%, –43%) for more than 420 ms at the same polarity. This feature protects the speaker from large DC currents or AC currents less than 2 Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at power-up until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults.

The minimum differential input voltages required to trigger the DC detect are show in table 2. The inputs must remain at or above the voltage listed in the table for more than 420 ms to trigger the DC detect.

Table 3. DC Detect Threshold

AV (dB) Vin (mV, differential)
20 112
26 56
32 28
36 17

7.3.6 PBTL Select

TPA3113D2 offers the feature of parallel BTL operation with two outputs of each channel connected directly. If the PBTL pin (pin 14) is tied high, the positive and negative outputs of each channel (left and right) are synchronized and in phase. To operate in this PBTL (mono) mode, apply the input signal to the RIGHT input and place the speaker between the LEFT and RIGHT outputs. Connect the positive and negative output together for best efficiency. For an example of the PBTL connection, see the schematic in Application and Implementation.

For normal BTL operation, connect the PBTL pin to local ground.

7.3.7 Short-Circuit Protection and Automatic Recovery Feature

TPA3113D2 has protection from overcurrent conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FAULT pin as a low state. The amplifier outputs are switched to a Hi-Z state when the short-circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through the low state.

If automatic recovery from the short-circuit protection latch is desired, connect the FAULT pin directly to the SD pin. This allows the FAULT pin function to automatically drive the SD pin low which clears the short-circuit protection latch.

7.3.8 Thermal Protection

Thermal protection on the TPA3113D2 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. When the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device begins normal operation at this point with no external system interaction.

Thermal protection faults are NOT reported on the FAULT terminal.

7.4 Device Functional Modes

7.4.1 TPA3113D2 Modulation Scheme

The TPA3113D2 uses a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The OUTP and OUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most of the switching period, reducing the switching current, which reduces any I2R losses in the load.

TPA3113D2 ai_vo_sch_los528.gif Figure 30. The TPA3113D2 Output Voltage and Current Waveforms Into an Inductive Load