SLOS743M August   2011  – March 2020 TRF7970A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Terminal Functions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
      1. 6.1.1 RFID and NFC Operation – Reader and Writer
      2. 6.1.2 NFC Device Operation – Initiator
      3. 6.1.3 NFC Device Operation – Target
        1. 6.1.3.1 Active Target
        2. 6.1.3.2 Passive Target
        3. 6.1.3.3 Card Emulation
    2. 6.2  System Block Diagram
    3. 6.3  Power Supplies
      1. 6.3.1 Supply Arrangements
      2. 6.3.2 Supply Regulator Settings
      3. 6.3.3 Power Modes
    4. 6.4  Receiver – Analog Section
      1. 6.4.1 Main and Auxiliary Receivers
      2. 6.4.2 Receiver Gain and Filter Stages
    5. 6.5  Receiver – Digital Section
      1. 6.5.1 Received Signal Strength Indicator (RSSI)
        1. 6.5.1.1 Internal RSSI – Main and Auxiliary Receivers
        2. 6.5.1.2 External RSSI
    6. 6.6  Oscillator Section
    7. 6.7  Transmitter – Analog Section
    8. 6.8  Transmitter – Digital Section
    9. 6.9  Transmitter – External Power Amplifier and Subcarrier Detector
    10. 6.10 TRF7970A IC Communication Interface
      1. 6.10.1 General Introduction
        1. 6.10.1.1 Continuous Address Mode
        2. 6.10.1.2 Noncontinuous Address Mode (Single Address Mode)
        3. 6.10.1.3 Direct Command Mode
        4. 6.10.1.4 FIFO Operation
      2. 6.10.2 Parallel Interface Mode
      3. 6.10.3 Reception of Air Interface Data
      4. 6.10.4 Data Transmission From MCU to TRF7970A
      5. 6.10.5 Serial Interface Communication (SPI)
        1. 6.10.5.1 Serial Interface Mode With Slave Select (SS)
      6. 6.10.6 Direct Mode
    11. 6.11 TRF7970A Initialization
    12. 6.12 Special Direct Mode for Improved MIFARE Compatibility
    13. 6.13 NFC Modes
      1. 6.13.1 Target
      2. 6.13.2 Initiator
    14. 6.14 Direct Commands from MCU to Reader
      1. 6.14.1 Command Codes
        1. 6.14.1.1  Idle (0x00)
        2. 6.14.1.2  Software Initialization (0x03)
        3. 6.14.1.3  Initial RF Collision Avoidance (0x04)
        4. 6.14.1.4  Response RF Collision Avoidance (0x05)
        5. 6.14.1.5  Response RF Collision Avoidance (0x06, n = 0)
        6. 6.14.1.6  Reset FIFO (0x0F)
        7. 6.14.1.7  Transmission With CRC (0x11)
        8. 6.14.1.8  Transmission Without CRC (0x10)
        9. 6.14.1.9  Delayed Transmission With CRC (0x13)
        10. 6.14.1.10 Delayed Transmission Without CRC (0x12)
        11. 6.14.1.11 Transmit Next Time Slot (0x14)
        12. 6.14.1.12 Block Receiver (0x16)
        13. 6.14.1.13 Enable Receiver (0x17)
        14. 6.14.1.14 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
        15. 6.14.1.15 Test External RF (RSSI at RX Input with TX OFF) (0x19)
    15. 6.15 Register Description
      1. 6.15.1 Register Preset
      2. 6.15.2 Register Overview
      3. 6.15.3 Detailed Register Description
        1. 6.15.3.1 Main Configuration Registers
          1. 6.15.3.1.1 Chip Status Control Register (0x00)
          2. 6.15.3.1.2 ISO Control Register (0x01)
        2. 6.15.3.2 Control Registers – Sublevel Configuration Registers
          1. 6.15.3.2.1  ISO/IEC 14443 TX Options Register (0x02)
          2. 6.15.3.2.2  ISO/IEC 14443 High-Bit-Rate and Parity Options Register (0x03)
          3. 6.15.3.2.3  TX Timer High Byte Control Register (0x04)
          4. 6.15.3.2.4  TX Timer Low Byte Control Register (0x05)
          5. 6.15.3.2.5  TX Pulse Length Control Register (0x06)
          6. 6.15.3.2.6  RX No Response Wait Time Register (0x07)
          7. 6.15.3.2.7  RX Wait Time Register (0x08)
          8. 6.15.3.2.8  Modulator and SYS_CLK Control Register (0x09)
          9. 6.15.3.2.9  RX Special Setting Register (0x0A)
          10. 6.15.3.2.10 Regulator and I/O Control Register (0x0B)
        3. 6.15.3.3 Status Registers
          1. 6.15.3.3.1  IRQ Status Register (0x0C)
          2. 6.15.3.3.2  Interrupt Mask Register (0x0D) and Collision Position Register (0x0E)
          3. 6.15.3.3.3  RSSI Levels and Oscillator Status Register (0x0F)
          4. 6.15.3.3.4  Special Functions Register (0x10)
          5. 6.15.3.3.5  Special Functions Register (0x11)
          6. 6.15.3.3.6  Adjustable FIFO IRQ Levels Register (0x14)
          7. 6.15.3.3.7  NFC Low Field Level Register (0x16)
          8. 6.15.3.3.8  NFCID1 Number Register (0x17)
          9. 6.15.3.3.9  NFC Target Detection Level Register (0x18)
          10. 6.15.3.3.10 NFC Target Protocol Register (0x19)
        4. 6.15.3.4 Test Registers
          1. 6.15.3.4.1 Test Register (0x1A)
          2. 6.15.3.4.2 Test Register (0x1B)
        5. 6.15.3.5 FIFO Control Registers
          1. 6.15.3.5.1 FIFO Status Register (0x1C)
          2. 6.15.3.5.2 TX Length Byte1 Register (0x1D), TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7970A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 Layout Considerations
    3. 7.3 Impedance Matching TX_Out (Pin 5) to 50 Ω
    4. 7.4 Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

6.1.3 NFC Device Operation – Target

The activation of NFC target is done when a sufficient RF field level is detected on the antenna. The level needed for wake-up is selectable and is stored in a nonvolatile register.

When the activation occurs, the system performs automatic power-up and waits for the first command to be received. Based on this command, the system knows if it should operate as passive or active target and at what bit rate. After activation, the receiver system offers the same analog features (for example, AGC, AM/PM, and bandwidth selection) as in the case of an RFID reader.

When used as the NFC target, the chip is typically in a power down or standby mode. If EN2 = H, the chip keeps the supply system on. If EN2 = L and EN = L, the chip is in complete power down. To operate as NFC target or card emulator, the MCU must load a value different from zero (0) in the Target Detection Level register (B0-B2) to enable the RF measurement system (supplied by VEXT, so it can also operate during complete power down and consume only 3.5 µA). The RF measurement constantly monitors the RF signal on the antenna input. When the RF level on the antenna input exceeds the level defined in the in Target Detection Level register, the chip is automatically activated (EN is internally forced high).

When the voltage supply system and the oscillator are started and are stable, osc_ok goes high (B6 of RSSI Level and Oscillator Status register) and IRQ is sent with bit B2 = 1 of IRQ register (field change). Bit B7 NFC Target Protocol in register directly displays the status of RF level detection (running constantly also during normal operation). This informs the MCU that the chip should start operation as NFC TARGET device. When the first command from the INITIATOR is received, another IRQ sent with B6 (RX start) set in the IRQ register. The MCU must set EN = H (confirm the power up) in the time between the two IRQs, because the internal power-up ends after the second IRQ. The type and coding of the first initiator (or reader in the case of a card emulator) command defines the communication protocol type that the target must use. Therefore, the communication protocol type is available in the NFC Target Protocol register immediately after receiving the first command.

Based on the first command from the INITIATOR, the following actions are taken:

  • If the first command is SENS_REQ or ALL_REQ, the TARGET must enter the SDD protocol for 106-kbps passive communication to begin; afterward, the baud rate can be changed to 212 kbps or 424 kbps, which is determined by the NFC initiator device. If bit B5 in the NFC Target Detection Level register is not set, the MCU handles the SDD and the command received is send to FIFO. For interoperability purposes, TI recommends allowing the MCU to handle the SDD process rather than use the TRF7970A Auto-SDD feature to ensure interoperability with other NFC devices. If the RF field is turned off (B7 in NFC Target Protocol register is low) at any time, the system sends an IRQ to the MCU with bit B2 (RF field change) in the IRQ register set high. This informs the MCU that the procedure was aborted and the system must be reset. The clock extractor is automatically activated in this mode.
  • If the command is SENS_REQ or ALL_REQ and the card emulation bit in ISO Control register is set, the system emulates an ISO/IEC 14443 A or ISO/IEC 14443 B tag. The procedure does not differ from the one previously described for the case of a passive target at 106 kbps. The clock extractor is automatically activated in this mode.
  • If the first command is a SENSF_REQ, the system becomes the TARGET in passive communication using 212 kbps or 424 kbps. The SDD is relatively simple and is handled by the MCU directly.
  • If the first command is ATR_REQ, the system operates as an active TARGET using the same communication speed and bit coding as used by the INITIATOR. Again, all of the replies are handled by the MCU. The MCU should handle the timing requirements for collision avoidance. This is done by using external RSSI to detect external RF fields before enabling RF on the TRF7970A.
  • If the first command is a SENSB_REQ request and the card emulation bit is set in the ISO Control register, the system enters ISO/IEC 14443 B emulation mode. The anticollision must be handled by the MCU, and the chip provides all physical level coding, decoding, and framing for this protocol.