SLOS781C July   2013  – November 2017 TAS5760LD

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Digital I/O Pins
    6. 6.6  Master Clock
    7. 6.7  Serial Audio Port
    8. 6.8  Protection Circuitry
    9. 6.9  Speaker Amplifier in All Modes
    10. 6.10 Speaker Amplifier in Stereo Bridge-Tied Load (BTL) Mode
    11. 6.11 Speaker Amplifier in Mono Parallel Bridge-Tied Load (PBTL) Mode
    12. 6.12 Headphone Amplifier and Line Driver
    13. 6.13 I²C Control Port
    14. 6.14 Typical Idle, Mute, Shutdown, Operational Power Consumption
    15. 6.15 Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode)
    16. 6.16 Typical Performance Characteristics (Mono PBTL Mode)
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
      2. 8.3.2 Speaker Amplifier Audio Signal Path
        1. 8.3.2.1 Serial Audio Port (SAP)
          1. 8.3.2.1.1 I²S Timing
          2. 8.3.2.1.2 Left-Justified
          3. 8.3.2.1.3 Right-Justified
        2. 8.3.2.2 DC Blocking Filter
        3. 8.3.2.3 Digital Boost and Volume Control
        4. 8.3.2.4 Digital Clipper
        5. 8.3.2.5 Closed-Loop Class-D Amplifier
      3. 8.3.3 Speaker Amplifier Protection Suite
        1. 8.3.3.1 Speaker Amplifier Fault Notification (SPK_FAULT Pin)
        2. 8.3.3.2 DC Detect Protection
      4. 8.3.4 Headphone and Line Driver Amplifier
    4. 8.4 Device Functional Modes
      1. 8.4.1 Hardware Control Mode
        1. 8.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 8.4.1.2 Serial Audio Port in Hardware Control Mode
        3. 8.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
        4. 8.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
        5. 8.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
        6. 8.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
        7. 8.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
        8. 8.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
          1. 8.4.1.8.1 Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
      2. 8.4.2 Software Control Mode
        1. 8.4.2.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 8.4.2.2 Serial Audio Port Controls
          1. 8.4.2.2.1 Serial Audio Port (SAP) Clocking
        3. 8.4.2.3 Parallel Bridge Tied Load Mode via Software Control
        4. 8.4.2.4 Speaker Amplifier Gain Structure
          1. 8.4.2.4.1 Speaker Amplifier Gain in Software Control Mode
          2. 8.4.2.4.2 Considerations for Setting the Speaker Amplifier Gain Structure
          3. 8.4.2.4.3 Recommendations for Setting the Speaker Amplifier Gain Structure in Software Control Mode
        5. 8.4.2.5 I²C Software Control Port
          1. 8.4.2.5.1 Setting the I²C Device Address
          2. 8.4.2.5.2 General Operation of the I²C Control Port
          3. 8.4.2.5.3 Writing to the I²C Control Port
          4. 8.4.2.5.4 Reading from the I²C Control Port
    5. 8.5 Register Maps
      1. 8.5.1 Control Port Registers - Quick Reference
      2. 8.5.2 Control Port Registers - Detailed Description
        1. 8.5.2.1  Device Identification Register (0x00)
        2. 8.5.2.2  Power Control Register (0x01)
        3. 8.5.2.3  Digital Control Register (0x02)
        4. 8.5.2.4  Volume Control Configuration Register (0x03)
        5. 8.5.2.5  Left Channel Volume Control Register (0x04)
        6. 8.5.2.6  Right Channel Volume Control Register (0x05)
        7. 8.5.2.7  Analog Control Register (0x06)
        8. 8.5.2.8  Reserved Register (0x07)
        9. 8.5.2.9  Fault Configuration and Error Status Register (0x08)
        10. 8.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
        11. 8.5.2.11 Digital Clipper Control 2 Register (0x10)
        12. 8.5.2.12 Digital Clipper Control 1 Register (0x11)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Stereo BTL Using Software Control
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Startup Procedures- Software Control Mode
          2. 9.2.1.2.2 Shutdown Procedures- Software Control Mode
          3. 9.2.1.2.3 Component Selection and Hardware Connections
            1. 9.2.1.2.3.1 I²C Pullup Resistors
            2. 9.2.1.2.3.2 Digital I/O Connectivity
          4. 9.2.1.2.4 Recommended Startup and Shutdown Procedures
          5. 9.2.1.2.5 Headphone and Line Driver Amplifier
            1. 9.2.1.2.5.1 Charge-Pump Flying Capacitor and DR_VSS Capacitor
            2. 9.2.1.2.5.2 Decoupling Capacitors
            3. 9.2.1.2.5.3 Gain-Setting Resistor Ranges
            4. 9.2.1.2.5.4 Using the Line Driver Amplifier in the TAS5760LD as a Second-Order Filter
            5. 9.2.1.2.5.5 External Undervoltage Detection
            6. 9.2.1.2.5.6 Input-Blocking Capacitors
          6. 9.2.1.2.6 Gain-Setting Resistors
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Stereo BTL Using Hardware Control
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Startup Procedures- Hardware Control Mode
          2. 9.2.2.2.2 Shutdown Procedures- Hardware Control Mode
          3. 9.2.2.2.3 Digital I/O Connectivity
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Mono PBTL Using Software Control
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
          1. 9.2.3.2.1 Startup Procedures- Software Control Mode
          2. 9.2.3.2.2 Shutdown Procedures- Software Control Mode
          3. 9.2.3.2.3 Component Selection and Hardware Connections
            1. 9.2.3.2.3.1 I²C Pull-Up Resistors
            2. 9.2.3.2.3.2 Digital I/O Connectivity
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Mono PBTL Using Hardware Control
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Startup Procedures- Hardware Control Mode
          2. 9.2.4.2.2 Shutdown Procedures- Hardware Control Mode
          3. 9.2.4.2.3 Component Selection and Hardware Connections
          4. 9.2.4.2.4 Digital I/O Connectivity
        3. 9.2.4.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 DVDD Supply
    2. 10.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB Footprint and Via Arrangement
            1. 11.1.3.2.1.1 Solder Stencil
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

These typical connection diagrams highlight the required external components and system level connections for proper operation of the device in several popular use cases.

Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in all available modes of operation. Additionally, some of the application circuits are available as reference designs and can be found on the TI website. Also see the TAS5760LD's product page for information on ordering the EVM. Not all configurations are available as reference designs; however, any design variation can be supported by TI through schematic and layout reviews. Visit support.ti.com for additional design assistance. Also, join the audio amplifier discussion forum at http://e2e.ti.com.

9.2 Typical Applications

These application circuits detail the recommended component selection and board configurations for the TAS5760LD device. Note that in Software Control mode, the clipping point of the amplifier and thus the rated power of the end equipment can be set using the digital clipper if desired. Additionally, if the sonic signature of the soft clipper is preferred, it can be used in addition to or in lieu of the digital clipper. The software control application circuit detailed in this section shows the soft clipper in its bypassed state, which results in a lower BOM count than when using the soft clipper. The trade-off between the sonic characteristics of the clipping events in the amplifier and BOM minimization can be chosen based upon the design goals related to the end product.

9.2.1 Stereo BTL Using Software Control

TAS5760LD TAC_48P_BTL_DR_SW.gif Figure 57. Stereo BTL Using Software Control

9.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 19 as the input parameters.

Table 19. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 5 V to 15 V
Host Processor I2S Compliant Master
I2C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speakers 4 Ω to 8 Ω

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Startup Procedures- Software Control Mode

  1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] = 11, ADR, etc.)
  2. Start with SPK_SD Pin = LOW
  3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
  4. Once power supplies are stable, start MCLK, SCLK, LRCK
  5. Configure the device via the control port in the manner required by the use case, making sure to mute the device via the control port
  6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD HIGH
  7. Unmute the device via the control port
  8. The device is now in normal operation

NOTE

Control port register changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.

9.2.1.2.2 Shutdown Procedures- Software Control Mode

  1. The device is in normal operation
  2. Mute via the control port
  3. Pull SPK_SD LOW
  4. The clocks can now be stopped and the power supplies brought down
  5. The device is now fully shutdown and powered off

NOTE

Any control port register changes excluding volume control changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.

9.2.1.2.3 Component Selection and Hardware Connections

Figure 57 details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

9.2.1.2.3.1 I²C Pullup Resistors

It is important to note that when the device is operated in Software Control Mode, the customary pullup resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, because they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification.

9.2.1.2.3.2 Digital I/O Connectivity

The digital I/O lines of the TAS5760LD are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

9.2.1.2.4 Recommended Startup and Shutdown Procedures

The start up and shutdown procedures for both Hardware Control Mode and Software Control Mode are shown below.

9.2.1.2.5 Headphone and Line Driver Amplifier

Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 58 illustrates the conventional line-driver amplifier connection to the load and output signal. DC blocking capacitors are often large in value. The line load (typical resistive values of 600 Ω to 10 kΩ) combines with the dc blocking capacitors to form a high-pass filter. Equation 3 shows the relationship between the load impedance (RL), the capacitor (CO), and the cutoff frequency (fC).

Equation 3. TAS5760LD E001_LOS681.gif

CO can be determined using Equation 4, where the load impedance and the cutoff frequency are known.

Equation 4. TAS5760LD E002_LOS681.gif

If fC is low, the capacitor must then have a large value because the load resistance is small. Large capacitance values require large package sizes. Large package sizes consume PCB area, stand high above the PCB, increase cost of assembly, and can reduce the fidelity of the audio output signal.

TAS5760LD line_dvr_LOS741.gif Figure 58. Conventional and DirectPath Line Drivers

The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user-provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split-supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. Combining this with the built-in click and pop reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors. The bottom block diagram and waveform of Figure 58 illustrate the ground-referenced line-driver architecture. This is the architecture of the headphone / line driver inside of the TAS5760LD.

9.2.1.2.5.1 Charge-Pump Flying Capacitor and DR_VSS Capacitor

The charge-pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The PVSS capacitor must be at least equal to the charge-pump capacitor in order to allow maximum charge transfer. Low-ESR capacitors are an ideal selection, and a value of 1 µF is typical. Capacitor values that are smaller than 1 µF can be used, but the maximum output voltage may be reduced and the device may not operate to specifications. If the TAS5760LD is used in highly noise-sensitive circuits, it is recommended to add a small LC filter on the DRVDD connection.

9.2.1.2.5.2 Decoupling Capacitors

The TAS5760LD contains a DirectPath line-driver amplifier that requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good, low equivalent-series-resistance (ESR) ceramic capacitor, typically 1 µF, placed as close as possible to the device DRVDD lead works best. Placing this decoupling capacitor close to the TAS5760LD is important for the performance of the amplifier. For filtering lower-frequency noise signals, a 10-µF or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device.

9.2.1.2.5.3 Gain-Setting Resistor Ranges

The gain-setting resistors, RIN and Rfb, must be chosen so that noise, stability, and input capacitor size of the headphone amplifier / line driver inside the TAS5760LD are kept within acceptable limits. Voltage gain is defined as Rfb divided by RIN.

Selecting values that are too low demands a large input ac-coupling capacitor, CIN. Selecting values that are too high increases the noise of the amplifier. Table 20 lists the recommended resistor values for different inverting-input gain settings.

Table 20. Recommended Resistor Values

GAIN INPUT RESISTOR VALUE, RIN FEEDBACK RESISTOR VALUE, Rfb
–1 V/V 10 kΩ 10 kΩ
–1.5 V/V 8.2 kΩ 12 kΩ
–2 V/V 15 kΩ 30 kΩ
–10 V/V 4.7 kΩ 47 kΩ

9.2.1.2.5.4 Using the Line Driver Amplifier in the TAS5760LD as a Second-Order Filter

Several audio DACs used today require an external low-pass filter to remove out-of-band noise. This is possible with the headphone amplifier / line driver inside the TAS5760LD, as it can be used like a standard operational amplifier. Several filter topologies can be implemented, both single-ended and differential. In Figure 59, multi-feedback (MFB) with differential input and single-ended input are shown.

An ac-coupling capacitor to remove dc content from the source is shown; it serves to block any dc content from the source and lowers the dc gain to 1, helping to reduce the output dc offset to a minimum.

The component values can be calculated with the help of the TI FilterPro™ program available on the TI Web site at: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html.

TAS5760LD lowpass_flt_LOS741.gif Figure 59. Second-Order Active Low-Pass Filter

The resistor values should have a low value for obtaining low noise, but should also have a high enough value to get a small-size ac-coupling capacitor. With the proposed values of R1 = 15 kΩ, R2 = 30 kΩ, and R3 = 43 kΩ, a dynamic range (DYR) of 106 dB can be achieved with a 1-mF input ac-coupling capacitor.

9.2.1.2.5.5 External Undervoltage Detection

External undervoltage detection can be used to mute/shut down the heaphone / line driver amplifier in the TAS5760LD before an input device can generate a pop. The shutdown threshold at the UVP pin is 1.25 V. The user selects a resistor divider to obtain the shutdown threshold and hysteresis for the specific application. The thresholds can be determined as follows:

Equation 5. VUVP = (1.25 – 6 µA × R3) × (R1 + R2) / R2
Equation 6. Hysteresis = 5 µA × R3 × (R1 + R2) / R2

For example, to obtain VUVP = 3.8 V and 1-V hysteresis, we can use R1 = 3 kΩ, R2 = 1 kΩ, and R3 = 50 kΩ.

TAS5760LD vol_det_LOS741.gif Figure 60. External Undervoltage Detection

9.2.1.2.5.6 Input-Blocking Capacitors

DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the headphone amplifier / line driver inside the TAS5760LD. These capacitors block the dc portion of the audio source and allow the headphone / line driver amplifier inside the TAS5760LD.

These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using Equation 7. For this calculation, the capacitance used is the input-blocking capacitor, and the resistance is the input resistor chosen from Table 20; then the frequency and/or capacitance can be determined when one of the two values is given.

It is recommended to use electrolytic capacitors or high-voltage-rated capacitors as input blocking capacitors to ensure minimal variation in capacitance with input voltages. Such variation in capacitance with input voltages is commonly seen in ceramic capacitors and can increase low-frequency audio distortion.

Equation 7. TAS5760LD E003_LOS681.gif

9.2.1.2.6 Gain-Setting Resistors

The gain-setting resistors, RIN and Rfb, must be placed close to their respective pins to minimize capacitive loading on these input pins and to ensure maximum stability of the headphone / line driver inside the TAS5760LD. For the recommended PCB layout, see the TAS5760LD EVM User's Guide, SLOU371.

9.2.1.3 Application Curves

Table 21. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 1. Output Power vs PVDD G001
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G024
Figure 5. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G027
Figure 7. Efficiency vs Output Power G030
Figure 8. Crosstalk vs Frequency G031
Figure 9. PVDD PSRR vs Frequency G019
Figure 10. DVDD PSRR vs Frequency G020
Figure 11. Idle Current Draw vs PVDD (Filterless) G042
Figure 12. Idle Current Draw vs PVDD (With LC Filter as Shown on the EVM) G023
Figure 13. Shutdown Current Draw vs PVDD (Filterless) G022
Figure 14. Output Power vs PVDD G039
Figure 15. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G002
Figure 18. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G008
Figure 20. Efficiency vs Output Power G014
Figure 21. Crosstalk vs Frequency G018
Figure 22. PVDD PSRR vs Frequency G019
Figure 23. Idle Current Draw vs PVDD (Filterless) G045
Figure 24. Idle Current Draw vs PVDD (With LC Filter as Shown on EVM) G044
Figure 25. Shutdown Current Draw vs PVDD (Filterless) G022

9.2.2 Stereo BTL Using Hardware Control

TAS5760LD TAC_48P_BTL_DR_HW.gif Figure 61. Stereo BTL Using Hardware Control

9.2.2.1 Design Requirements

For this design example, use the parameters listed in Table 22 as the input parameters.

Table 22. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 5 V to 15 V
Host Processor I2S Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speakers 4 Ω to 8 Ω

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Startup Procedures- Hardware Control Mode

  1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ, GAIN, etc.)
  2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH
  3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
  4. Once power supplies are stable, start MCLK, SCLK, LRCK
  5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring SPK_SD HIGH
  6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW
  7. The device is now in normal operation

9.2.2.2.2 Shutdown Procedures- Hardware Control Mode

  1. The device is in normal operation
  2. Pull SPK_SLEEP/ADR HIGH
  3. Pull SPK_SD LOW
  4. The clocks can now be stopped and the power supplies brought down
  5. The device is now fully shutdown and powered off

9.2.2.2.3 Digital I/O Connectivity

The digital I/O lines of the TAS5760LD are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

9.2.2.3 Application Curves

Table 23. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 1. Output Power vs PVDD G001
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G024
Figure 4. Idle Channel Noise vs PVDD G026
Figure 5. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G027
Figure 7. Efficiency vs Output Power G030
Figure 8. Crosstalk vs Frequency G031
Figure 9. PVDD PSRR vs Frequency G019
Figure 10. DVDD PSRR vs Frequency G020
Figure 11. Idle Current Draw vs PVDD (Filterless) G042
Figure 12. Idle Current Draw vs PVDD (With LC Filter as Shown on the EVM) G023
Figure 13. Shutdown Current Draw vs PVDD (Filterless) G022
Figure 14. Output Power vs PVDD G039
Figure 15. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G002
Figure 17. Idle Channel Noise vs PVDD G006
Figure 18. THD+N vs Output Power With PVDD = 12 V, Both Channels Driven G008
Figure 20. Efficiency vs Output Power G014
Figure 21. Crosstalk vs Frequency G018
Figure 22. PVDD PSRR vs Frequency G019
Figure 23. Idle Current Draw vs PVDD (Filterless) G045
Figure 24. Idle Current Draw vs PVDD (With LC Filter as Shown on EVM) G044
Figure 25. Shutdown Current Draw vs PVDD (Filterless) G022

9.2.3 Mono PBTL Using Software Control

TAS5760LD TAC_48P_PBTL_DR_SW.gif TAS5760LD mono_pbtl_sw_ctrl2.gif Figure 62. Mono PBTL Using Software Control

9.2.3.1 Design Requirements

For this design example, use the parameters listed in Table 24 as the input parameters.

Table 24. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 5 V to 15 V
Host Processor I2S Compliant Master
I2C Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speakers 4 Ω to 8 Ω

9.2.3.2 Detailed Design Procedure

9.2.3.2.1 Startup Procedures- Software Control Mode

  1. Configure all digital I/O pins as required by the application using PCB connections (that is SPK_GAIN[1:0] = 11, ADR, etc.)
  2. Start with SPK_SD Pin = LOW
  3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
  4. Once power supplies are stable, start MCLK, SCLK, LRCK
  5. Configure the device via the control port in the manner required by the use case, making sure to mute the device via the control port
  6. Once power supplies and clocks are stable and the control port has been programmed, bring SPK_SD HIGH
  7. Unmute the device via the control port
  8. The device is now in normal operation

NOTE

Control port register changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.

9.2.3.2.2 Shutdown Procedures- Software Control Mode

  1. The device is in normal operation
  2. Mute via the control port
  3. Pull SPK_SD LOW
  4. The clocks can now be stopped and the power supplies brought down
  5. The device is now fully shutdown and powered off

NOTE

Any control port register changes excluding volume control changes should only occur when the device is placed into shutdown. This can be accomplished either by pulling the SPK_SD pin LOW or clearing the SPK_SD bit in the control port.

9.2.3.2.3 Component Selection and Hardware Connections

Figure 62 above details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

9.2.3.2.3.1 I²C Pull-Up Resistors

It is important to note that when the device is operated in Software Control Mode, the customary pull-up resistors are required on the SCL and SDA signal lines. They are not shown in the Typical Application Circuits, since they are shared by all of the devices on the I²C bus and are considered to be part of the associated passive components for the System Processor. These resistor values should be chosen per the guidance provided in the I²C Specification.

9.2.3.2.3.2 Digital I/O Connectivity

The digital I/O lines of the TAS5760LD are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

9.2.3.3 Application Curves

Table 25. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 27. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G032
Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input G035
Figure 37. Efficiency vs Output Power G038
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G004
Figure 35. THD+N vs Output Power With PVDD = 12 V G011
Figure 7. Efficiency vs Output Power G015

9.2.4 Mono PBTL Using Hardware Control

TAS5760LD TAC_48P_PBTL_DR_HW.gif TAS5760LD mono_pbtl_hw_ctrl.gif Figure 63. Mono PBTL Using Hardware Control

9.2.4.1 Design Requirements

For this design example, use the parameters listed in Table 26 as the input parameters.

Table 26. Design Parameters

PARAMETER EXAMPLE
Low Power Supply 3.3 V
High Power Supply 5 V to 15 V
Host Processor I2S Compliant Master
GPIO Control
Output Filters Inductor-Capacitor Low Pass Filter
Speakers 4 Ω to 8 Ω

9.2.4.2 Detailed Design Procedure

9.2.4.2.1 Startup Procedures- Hardware Control Mode

  1. Configure all hardware pins as required by the application using PCB connections (that is PBTL, FREQ, GAIN, etc.)
  2. Start with SPK_SD pin pulled LOW and SPK_SLEEP/ADR pin pulled HIGH
  3. Bring up power supplies (it does not matter if PVDD/AVDD or DVDD comes up first, provided the device is held in shutdown.)
  4. Once power supplies are stable, start MCLK, SCLK, LRCK
  5. Once power supplies and clocks are stable and all hardware control pins have been configured, bring SPK_SD HIGH
  6. Once the device is out of shutdown mode, bring SPK_SLEEP/ADR LOW
  7. The device is now in normal operation

9.2.4.2.2 Shutdown Procedures- Hardware Control Mode

  1. The device is in normal operation
  2. Pull SPK_SLEEP/ADR HIGH
  3. Pull SPK_SD LOW
  4. The clocks can now be stopped and the power supplies brought down
  5. The device is now fully shutdown and powered off

9.2.4.2.3 Component Selection and Hardware Connections

Figure 63 details the typical connections required for proper operation of the device. It is with this list of components that the device was simulated, tested, and characterized. Deviation from this typical application circuit unless recommended by this document may produce unwanted results, which could range from degradation of audio performance to destructive failure of the device.

9.2.4.2.4 Digital I/O Connectivity

The digital I/O lines of the TAS5760LD are described in previous sections. As discussed, whenever a static digital pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

9.2.4.3 Application Curve

Table 27. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 32. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G032
Figure 34. Idle Channel Noise vs PVDD G034
Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input G035
Figure 37. Efficiency vs Output Power G038
Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W G004
Figure 17. Idle Channel Noise vs PVDD G007
Figure 35. THD+N vs Output Power With PVDD = 12 V G011
Figure 7. Efficiency vs Output Power G015