SLOS782C July   2013  – May  2017 TAS5760L

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Digital I/O Pins
    6. 7.6  Master Clock
    7. 7.7  Serial Audio Port
    8. 7.8  Protection Circuitry
    9. 7.9  Speaker Amplifier in All Modes
    10. 7.10 Speaker Amplifier in Stereo Bridge-Tied Load (BTL) Mode
    11. 7.11 Speaker Amplifier in Mono Parallel Bridge-Tied Load (PBTL) Mode
    12. 7.12 I²C Control Port
    13. 7.13 Typical Idle, Mute, Shutdown, Operational Power Consumption
    14. 7.14 Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode)
    15. 7.15 Typical Performance Characteristics (Mono PBTL Mode)
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Speaker Amplifier Audio Signal Path
        1. 9.3.2.1 Serial Audio Port (SAP)
          1. 9.3.2.1.1 I²S Timing
          2. 9.3.2.1.2 Left-Justified
          3. 9.3.2.1.3 Right-Justified
        2. 9.3.2.2 DC Blocking Filter
        3. 9.3.2.3 Digital Boost and Volume Control
        4. 9.3.2.4 Digital Clipper
        5. 9.3.2.5 Closed-Loop Class-D Amplifier
      3. 9.3.3 Speaker Amplifier Protection Suite
        1. 9.3.3.1 Speaker Amplifier Fault Notification (SPK_FAULT Pin)
        2. 9.3.3.2 DC Detect Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Hardware Control Mode
        1. 9.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 9.4.1.2 Serial Audio Port in Hardware Control Mode
        3. 9.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
        4. 9.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
        5. 9.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
        6. 9.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
        7. 9.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
        8. 9.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
          1. 9.4.1.8.1 Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
      2. 9.4.2 Software Control Mode
        1. 9.4.2.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 9.4.2.2 Serial Audio Port Controls
          1. 9.4.2.2.1 Serial Audio Port (SAP) Clocking
        3. 9.4.2.3 Parallel Bridge Tied Load Mode via Software Control
        4. 9.4.2.4 Speaker Amplifier Gain Structure
          1. 9.4.2.4.1 Speaker Amplifier Gain in Software Control Mode
          2. 9.4.2.4.2 Considerations for Setting the Speaker Amplifier Gain Structure
          3. 9.4.2.4.3 Recommendations for Setting the Speaker Amplifier Gain Structure in Software Control Mode
        5. 9.4.2.5 I²C Software Control Port
          1. 9.4.2.5.1 Setting the I²C Device Address
          2. 9.4.2.5.2 General Operation of the I²C Control Port
          3. 9.4.2.5.3 Writing to the I²C Control Port
          4. 9.4.2.5.4 Reading from the I²C Control Port
    5. 9.5 Register Maps
      1. 9.5.1 Control Port Registers - Quick Reference
      2. 9.5.2 Control Port Registers - Detailed Description
        1. 9.5.2.1  Device Identification Register (0x00)
        2. 9.5.2.2  Power Control Register (0x01)
        3. 9.5.2.3  Digital Control Register (0x02)
        4. 9.5.2.4  Volume Control Configuration Register (0x03)
        5. 9.5.2.5  Left Channel Volume Control Register (0x04)
        6. 9.5.2.6  Right Channel Volume Control Register (0x05)
        7. 9.5.2.7  Analog Control Register (0x06)
        8. 9.5.2.8  Reserved Register (0x07)
        9. 9.5.2.9  Fault Configuration and Error Status Register (0x08)
        10. 9.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
        11. 9.5.2.11 Digital Clipper Control 2 Register (0x10)
        12. 9.5.2.12 Digital Clipper Control 1 Register (0x11)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Using Software Control
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Startup Procedures- Software Control Mode
          2. 10.2.1.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.1.2.3 Component Selection and Hardware Connections
            1. 10.2.1.2.3.1 I²C Pullup Resistors
            2. 10.2.1.2.3.2 Digital I/O Connectivity
          4. 10.2.1.2.4 Recommended Startup and Shutdown Procedures
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Stereo BTL Using Hardware Control
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.2.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.2.2.3 Digital I/O Connectivity
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Mono PBTL Using Software Control
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
          1. 10.2.3.2.1 Startup Procedures- Software Control Mode
          2. 10.2.3.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.3.2.3 Component Selection and Hardware Connections
            1. 10.2.3.2.3.1 I²C Pull-Up Resistors
            2. 10.2.3.2.3.2 Digital I/O Connectivity
        3. 10.2.3.3 Application Curve
      4. 10.2.4 Mono PBTL Using Hardware Control
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
          1. 10.2.4.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.4.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.4.2.3 Component Selection and Hardware Connections
          4. 10.2.4.2.4 Digital I/O Connectivity
        3. 10.2.4.3 Application Curve
      5. 10.2.5 Stereo BTL Using Software Control, 32-Pin DAP Package Option
        1. 10.2.5.1 Design Requirements
        2. 10.2.5.2 Detailed Design Procedure
          1. 10.2.5.2.1 Startup Procedures- Software Control Mode
          2. 10.2.5.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.5.2.3 Component Selection and Hardware Connections
            1. 10.2.5.2.3.1 I²C Pullup Resistors
            2. 10.2.5.2.3.2 Digital I/O Connectivity
          4. 10.2.5.2.4 Recommended Startup and Shutdown Procedures
        3. 10.2.5.3 Application Curve
      6. 10.2.6 Stereo BTL Using Hardware Control, 32-Pin DAP Package Option
        1. 10.2.6.1 Design Requirements
        2. 10.2.6.2 Detailed Design Procedure
          1. 10.2.6.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.6.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.6.2.3 Digital I/O Connectivity
        3. 10.2.6.3 Application Curve
      7. 10.2.7 Mono PBTL Using Software Control, 32-Pin DAP Package Option
        1. 10.2.7.1 Design Requirements
        2. 10.2.7.2 Detailed Design Procedure
          1. 10.2.7.2.1 Startup Procedures- Software Control Mode
          2. 10.2.7.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.7.2.3 Component Selection and Hardware Connections
            1. 10.2.7.2.3.1 I²C Pull-Up Resistors
            2. 10.2.7.2.3.2 Digital I/O Connectivity
        3. 10.2.7.3 Application Curve
      8. 10.2.8 Mono PBTL Using Hardware Control, 32-Pin DAP Package Option
        1. 10.2.8.1 Design Requirements
        2. 10.2.8.2 Detailed Design Procedure
          1. 10.2.8.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.8.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.8.2.3 Component Selection and Hardware Connections
          4. 10.2.8.2.4 Digital I/O Connectivity
        3. 10.2.8.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 DVDD Supply
    2. 11.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. 12.1.3.1 Device, Copper, and Component Layout
        2. 12.1.3.2 Stencil Pattern
          1. 12.1.3.2.1 PCB Footprint and Via Arrangement
            1. 12.1.3.2.1.1 Solder Stencil
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

12 Layout

12.1 Layout Guidelines

12.1.1 General Guidelines for Audio Amplifiers

Audio amplifiers which incorporate switching output stages must have special attention paid to their layout and the layout of the supporting components used around them. The system level performance metrics, including thermal performance, electromagnetic compliance (EMC), device reliability, and audio performance are all affected by the device and supporting component layout. Ideally, the guidance provided in the applications section with regard to device and component selection can be followed by precise adherence to the layout guidance shown in Layout Example. These examples represent exemplary baseline balance of the engineering trade-offs involved with laying out the device. These designs can be modified slightly as needed to meet the needs of a given application. In some applications, for instance, solution size can be compromised in order to improve thermal performance through the use of additional contiguous copper near the device. Conversely, EMI performance can be prioritized over thermal performance by routing on internal traces and incorporating a via picket-fence and additional filtering components. In all cases, it is recommended to start from the guidance shown in the Layout Example section and the TAS5760xx EVM, and work with TI field application engineers or through the E2E community in order to modify it based upon the application specific goals.

12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network

Placing the bypassing and decoupling capacitors close to supply has been long understood in the industry. This applies to DVDD, DRVDD, and PVDD. However, the capacitors on the PVDD net for the TAS5760L device deserve special attention. It is imperative that the small bypass capacitors on the PVDD lines of the DUT be placed as close the PVDD pins as possible. Not only does placing these devices far away from the pins increase the electromagnetic interference in the system, but doing so can also negatively affect the reliability of the device. Placement of these components too far from the TAS5760Ldevice may cause ringing on the output pins that can cause the voltage on the output pin to exceed the maximum allowable ratings shown in the Absolute Maximum Ratings table, damaging the device. For that reason, the capacitors on the PVDD net must be no further away from their associated PVDD pins than what is shown in the example layouts in the Layout Example section.

12.1.3 Optimizing Thermal Performance

Follow the layout examples shown in the Layout Example section of this document to achieve the best balance of solution size, thermal, audio, and electromagnetic performance. In some cases, deviation from this guidance may be required due to design constraints which cannot be avoided. In these instances, the system designer should ensure that the heat can get out of the device and into the ambient air surrounding the device. Fortunately, the heat created in the device would prefer to travel away from the device and into the lower temperature structures around the device.

12.1.3.1 Device, Copper, and Component Layout

Primarily, the goal of the PCB design is to minimize the thermal impedance in the path to those cooler structures. These tips should be followed to achieve that goal:

  • Avoid placing other heat producing components or structures near the amplifier (including above or below in the end equipment).
  • If possible, use a higher layer count PCB to provide more heat sinking capability for the TAS5760Ldevice and to prevent traces and copper signal and power planes from breaking up the contiguous copper on the top and bottom layer.
  • Place the TTAS5760L device away from the edge of the PCB when possible to ensure that heat can travel away from the device on all four sides.
  • Avoid cutting off the flow of heat from the TAS5760Ldevice to the surrounding areas with traces or via strings. Instead, route traces perpendicular to the device and line up vias in columns which are perpendicular to the device.
  • Unless the area between two pads of a passive component is large enough to allow copper to flow in between the two pads, orient it so that the narrow end of the passive component is facing the TAS5760L device.
  • Because the ground pins are the best conductors of heat in the package, maintain a contiguous ground plane from the ground pins to the PCB area surrounding the device for as many of the ground pins as possible.

12.1.3.2 Stencil Pattern

The recommended drawings for the TAS5760L device PCB foot print and associated stencil pattern are shown at the end of this document in the package addendum. Additionally, baseline recommendations for the via arrangement under and around the device are given as a starting point for the PCB design. This guidance is provided to suit the majority of manufacturing capabilities in the industry and prioritizes manufacturability over all other performance criteria. In elevated ambient temperatures or under high-power dissipation use-cases, this guidance may be too conservative and advanced PCB design techniques may be used to improve thermal performance of the system. It is important to note that the customer must verify that deviation from the guidance shown in the package addendum, including the deviation explained in this section, meets the customer’s quality, reliability, and manufacturability goals.

12.1.3.2.1 PCB Footprint and Via Arrangement

The PCB footprint (also known as a symbol or land pattern) communicates to the PCB fabrication vendor the shape and position of the copper patterns to which the TAS5760Ldevice will be soldered to. This footprint can be followed directly from the guidance in the package addendum at the end of this data sheet. It is important to make sure that the thermal pad, which connects electrically and thermally to the PowerPAD of the TAS5760Ldevice, be made no smaller than what is specified in the package addendum. This ensures that the TAS5760L device has the largest interface possible to move heat from the device to the board. The via pattern shown in the package addendum provides an improved interface to carry the heat from the device through to the layers of the PCB, because small diameter plated vias (with minimally-sized annular rings) present a low thermal-impedance path from the device into the PCB. Once into the PCB, the heat travels away from the device and into the surrounding structures and air. By increasing the number of vias, as shown in Layout Example, this interface can benefit from improved thermal performance.

NOTE

Vias can obstruct heat flow if they are not constructed properly.
  • Remove thermal reliefs on thermal vias, because they impede the flow of heat through the via.
  • Vias filled with thermally conductive material are best, but a simple plated via can be used to avoid the additional cost of filled vias.
  • The drill diameter should be no more than 8mils in diameter. Also, the distance between the via barrel and the surrounding planes should be minimized to help heat flow from the via into the surrounding copper material. In all cases, minimum spacing should be determined by the voltages present on the planes surrounding the via and minimized wherever possible.
  • Vias should be arranged in columns, which extend in a line radially from the heat source to the surrounding area. This arrangement is shown in the Layout Example section.
  • Ensure that vias do not cut-off power current flow from the power supply through the planes on internal layers. If needed, remove some vias which are farthest from the TAS5760L device to open up the current path to and from the device.

12.1.3.2.1.1 Solder Stencil

During the PCB assembly process, a piece of metal called a stencil on top of the PCB and deposits solder paste on the PCB wherever there is an opening (called an aperture) in the stencil. The stencil determines the quantity and the location of solder paste that is applied to the PCB in the electronic manufacturing process. In most cases, the aperture for each of the component pads is almost the same size as the pad itself.

However, the thermal pad on the PCB is quite large and depositing a large, single deposition of solder paste would lead to manufacturing issues. Instead, the solder is applied to the board in multiple apertures, to allow the solder paste to outgas during the assembly process and reduce the risk of solder bridging under the device. This structure is called an aperture array, and is shown in the Layout Example section. It is important that the total area of the aperture array (the area of all of the small apertures combined) covers between 70% and 80% of the area of the thermal pad itself.

12.2 Layout Example

TAS5760L PBTL_layout.gif Figure 65. DAP Package PBTL Configuration
TAS5760L DAP_btl_lo.gif Figure 66. DAP Package BTL Configuration
TAS5760L DCA_layout.gif Figure 67. DCA Package PBTL Configuration
TAS5760L dca_btl.gif Figure 68. DCA Package BTL Configuration