SLOS782C July   2013  – May  2017 TAS5760L

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Digital I/O Pins
    6. 7.6  Master Clock
    7. 7.7  Serial Audio Port
    8. 7.8  Protection Circuitry
    9. 7.9  Speaker Amplifier in All Modes
    10. 7.10 Speaker Amplifier in Stereo Bridge-Tied Load (BTL) Mode
    11. 7.11 Speaker Amplifier in Mono Parallel Bridge-Tied Load (PBTL) Mode
    12. 7.12 I²C Control Port
    13. 7.13 Typical Idle, Mute, Shutdown, Operational Power Consumption
    14. 7.14 Typical Speaker Amplifier Performance Characteristics (Stereo BTL Mode)
    15. 7.15 Typical Performance Characteristics (Mono PBTL Mode)
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Speaker Amplifier Audio Signal Path
        1. 9.3.2.1 Serial Audio Port (SAP)
          1. 9.3.2.1.1 I²S Timing
          2. 9.3.2.1.2 Left-Justified
          3. 9.3.2.1.3 Right-Justified
        2. 9.3.2.2 DC Blocking Filter
        3. 9.3.2.3 Digital Boost and Volume Control
        4. 9.3.2.4 Digital Clipper
        5. 9.3.2.5 Closed-Loop Class-D Amplifier
      3. 9.3.3 Speaker Amplifier Protection Suite
        1. 9.3.3.1 Speaker Amplifier Fault Notification (SPK_FAULT Pin)
        2. 9.3.3.2 DC Detect Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Hardware Control Mode
        1. 9.4.1.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 9.4.1.2 Serial Audio Port in Hardware Control Mode
        3. 9.4.1.3 Soft Clipper Control (SFT_CLIP Pin)
        4. 9.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)
        5. 9.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)
        6. 9.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)
        7. 9.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)
        8. 9.4.1.8 Considerations for Setting the Speaker Amplifier Gain Structure
          1. 9.4.1.8.1 Recommendations for Setting the Speaker Amplifier Gain Structure in Hardware Control Mode
      2. 9.4.2 Software Control Mode
        1. 9.4.2.1 Speaker Amplifier Shut Down (SPK_SD Pin)
        2. 9.4.2.2 Serial Audio Port Controls
          1. 9.4.2.2.1 Serial Audio Port (SAP) Clocking
        3. 9.4.2.3 Parallel Bridge Tied Load Mode via Software Control
        4. 9.4.2.4 Speaker Amplifier Gain Structure
          1. 9.4.2.4.1 Speaker Amplifier Gain in Software Control Mode
          2. 9.4.2.4.2 Considerations for Setting the Speaker Amplifier Gain Structure
          3. 9.4.2.4.3 Recommendations for Setting the Speaker Amplifier Gain Structure in Software Control Mode
        5. 9.4.2.5 I²C Software Control Port
          1. 9.4.2.5.1 Setting the I²C Device Address
          2. 9.4.2.5.2 General Operation of the I²C Control Port
          3. 9.4.2.5.3 Writing to the I²C Control Port
          4. 9.4.2.5.4 Reading from the I²C Control Port
    5. 9.5 Register Maps
      1. 9.5.1 Control Port Registers - Quick Reference
      2. 9.5.2 Control Port Registers - Detailed Description
        1. 9.5.2.1  Device Identification Register (0x00)
        2. 9.5.2.2  Power Control Register (0x01)
        3. 9.5.2.3  Digital Control Register (0x02)
        4. 9.5.2.4  Volume Control Configuration Register (0x03)
        5. 9.5.2.5  Left Channel Volume Control Register (0x04)
        6. 9.5.2.6  Right Channel Volume Control Register (0x05)
        7. 9.5.2.7  Analog Control Register (0x06)
        8. 9.5.2.8  Reserved Register (0x07)
        9. 9.5.2.9  Fault Configuration and Error Status Register (0x08)
        10. 9.5.2.10 Reserved Controls (9 / 0x09) - (15 / 0x0F)
        11. 9.5.2.11 Digital Clipper Control 2 Register (0x10)
        12. 9.5.2.12 Digital Clipper Control 1 Register (0x11)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Using Software Control
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Startup Procedures- Software Control Mode
          2. 10.2.1.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.1.2.3 Component Selection and Hardware Connections
            1. 10.2.1.2.3.1 I²C Pullup Resistors
            2. 10.2.1.2.3.2 Digital I/O Connectivity
          4. 10.2.1.2.4 Recommended Startup and Shutdown Procedures
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Stereo BTL Using Hardware Control
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.2.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.2.2.3 Digital I/O Connectivity
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Mono PBTL Using Software Control
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
          1. 10.2.3.2.1 Startup Procedures- Software Control Mode
          2. 10.2.3.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.3.2.3 Component Selection and Hardware Connections
            1. 10.2.3.2.3.1 I²C Pull-Up Resistors
            2. 10.2.3.2.3.2 Digital I/O Connectivity
        3. 10.2.3.3 Application Curve
      4. 10.2.4 Mono PBTL Using Hardware Control
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
          1. 10.2.4.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.4.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.4.2.3 Component Selection and Hardware Connections
          4. 10.2.4.2.4 Digital I/O Connectivity
        3. 10.2.4.3 Application Curve
      5. 10.2.5 Stereo BTL Using Software Control, 32-Pin DAP Package Option
        1. 10.2.5.1 Design Requirements
        2. 10.2.5.2 Detailed Design Procedure
          1. 10.2.5.2.1 Startup Procedures- Software Control Mode
          2. 10.2.5.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.5.2.3 Component Selection and Hardware Connections
            1. 10.2.5.2.3.1 I²C Pullup Resistors
            2. 10.2.5.2.3.2 Digital I/O Connectivity
          4. 10.2.5.2.4 Recommended Startup and Shutdown Procedures
        3. 10.2.5.3 Application Curve
      6. 10.2.6 Stereo BTL Using Hardware Control, 32-Pin DAP Package Option
        1. 10.2.6.1 Design Requirements
        2. 10.2.6.2 Detailed Design Procedure
          1. 10.2.6.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.6.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.6.2.3 Digital I/O Connectivity
        3. 10.2.6.3 Application Curve
      7. 10.2.7 Mono PBTL Using Software Control, 32-Pin DAP Package Option
        1. 10.2.7.1 Design Requirements
        2. 10.2.7.2 Detailed Design Procedure
          1. 10.2.7.2.1 Startup Procedures- Software Control Mode
          2. 10.2.7.2.2 Shutdown Procedures- Software Control Mode
          3. 10.2.7.2.3 Component Selection and Hardware Connections
            1. 10.2.7.2.3.1 I²C Pull-Up Resistors
            2. 10.2.7.2.3.2 Digital I/O Connectivity
        3. 10.2.7.3 Application Curve
      8. 10.2.8 Mono PBTL Using Hardware Control, 32-Pin DAP Package Option
        1. 10.2.8.1 Design Requirements
        2. 10.2.8.2 Detailed Design Procedure
          1. 10.2.8.2.1 Startup Procedures- Hardware Control Mode
          2. 10.2.8.2.2 Shutdown Procedures- Hardware Control Mode
          3. 10.2.8.2.3 Component Selection and Hardware Connections
          4. 10.2.8.2.4 Digital I/O Connectivity
        3. 10.2.8.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 DVDD Supply
    2. 11.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. 12.1.3.1 Device, Copper, and Component Layout
        2. 12.1.3.2 Stencil Pattern
          1. 12.1.3.2.1 PCB Footprint and Via Arrangement
            1. 12.1.3.2.1.1 Solder Stencil
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

11 Power Supply Recommendations

The TAS5760L device requires two power supplies for proper operation. A high-voltage supply called PVDD is required to power the output stage of the speaker amplifier and its associated circuitry. Additionally, one low voltage power supply called DVDD is required to power the various low-power portions of the device. The allowable voltage range for both the PVDD and the DVDD supply are listed in the Recommended Operating Conditions table.

11.1 DVDD Supply

The DVDD supply required from the system is used to power several portions of the device it provides power to the DVDD pin and the DRVDD pin. Proper connection, routing, and decoupling techniques are highlighted in the TAS5760xx EVM User's Guide, SLOU371 (as well as the Application and Implementation section and Layout Example section) and must be followed as closely as possible for proper operation and performance. Deviation from the guidance offered in the TAS5760xx EVM User's Guide, which followed the same techniques as those shown in the Application and Implementation section, may result in reduced performance, errant functionality, or even damage to the TTAS5760L device. Some portions of the device also require a separate power supply which is a lower voltage than the DVDD supply. To simplify the power supply requirements for the system, the TAS5760L device includes an integrated low-dropout (LDO) linear regulator to create this supply. This linear regulator is internally connected to the DVDD supply and its output is presented on the ANA_REG pin, providing a connection point for an external bypass capacitor. It is important to note that the linear regulator integrated in the device has only been designed to support the current requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the device.

11.2 PVDD Supply

The output stage of the speaker amplifier drives the load using the PVDD supply. This is the power supply which provides the drive current to the load during playback. Proper connection, routing, and decoupling techniques are highlighted in the TAS5760xx EVM and must be followed as closely as possible for proper operation and performance. Due the high-voltage switching of the output stage, it is particularly important to properly decouple the output power stages in the manner described in the TaS5760xx EVM User's Guide, SLOU371. The lack of proper decoupling, like that shown in the EVM User's Guide, can results in voltage spikes which can damage the device. A separate power supply is required to drive the gates of the MOSFETs used in the output stage of the speaker amplifier. This power supply is derived from the PVDD supply via an integrated linear regulator. A GVDD_REG pin is provided for the attachment of decoupling capacitor for the gate drive voltage regulator. It is important to note that the linear regulator integrated in the device has only been designed to support the current requirements of the internal circuitry, and should not be used to power any additional external circuitry. Additional loading on this pin could cause the voltage to sag, negatively affecting the performance and operation of the device.