SLOS821B June   2013  – September 2014 TPA6133A2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Application Diagram
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specification
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Headphone Amplifiers
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modes of Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input-Blocking Capacitors
        2. 9.2.2.2 Charge Pump Flying Capacitor and CPVSS Capacitor
        3. 9.2.2.3 Decoupling Capacitors
        4. 9.2.2.4 Optional Test Setup
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelimes
      1. 11.1.1 Exposed Pad On TPA6133A2RTJ Package
      2. 11.1.2 GND Connections
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

RTJ Package
(Top VIEW)
Pinout_slos821.gif

Pin Functions

PIN INPUT, OUTPUT, POWER DESCRIPTION
NAME NUMBER
LEFTINM 1 I Left channel negative differential input. Impedance must be matched to LEFTINP. Connect the left input to LEFTINM when using single-ended inputs.
LEFTINP 2 I Left channel positive differential input. Impedance must be matched to LEFTINM. AC ground LEFTINP near signal source while maintaining matched impedance to LEFTINM when using single-ended inputs.
RIGHTINP 4 I Right channel positive differential input. Impedance must be matched to RIGHTINM. AC ground RIGHTINP near signal source while maintaining matched impedance to RIGHTINM when using single-ended inputs.
GND 3, 9, 10, 13 P Analog ground. Must be connected to common supply GND. It is recommended that this pin be used to decouple VDD for analog. Use pin 13 to decouple pin 12 on the QFN package.
RIGHTINM 5 I Right channel negative differential input. Impedance must be matched to RIGHTINP. Connect the right input to RIGHTINM when using single-ended inputs.
SD 6 I Shutdown. Active low logic. 5V tolerant input.
TEST2 7 I Factory test pins. Pull up to VDD supply. See Applications Diagram.
TEST1 8 I Factory test pins. Pull up to VDD supply. See Applications Diagram.
HPRIGHT 11 O Headphone light channel output. Connect to the right terminal of the headphone jack.
VDD 12 P Analog VDD. VDD must be connected to common VDD supply. Decouple with its own 1-μF capacitor to analog ground (pin 13).
HPLEFT 14 O Headphone left channel output. Connect to left terminal of headphone jack.
CPVSS 15, 16 P Negative supply generated by the charge pump. Decouple to pin 19 or a GND plane. Use a 1 μF capacitor.
CPN 17 P Charge pump flying capacitor negative terminal. Connect one side of the flying capacitor to CPN.
CPP 18 P Charge pump flying capacitor positive terminal. Connect one side of the flying capacitor to CPP.
GND 19 P Charge pump ground. GND must be connected to common supply GND. It is recommended that this pin be decoupled to the VDD of the charge pump pin (pin 20 on the QFN).
VDD 20 P Charge pump voltage supply. VDD must be connected to the common VDD voltage supply. Decouple to GND (pin 19 ) with its own 1 μF capacitor.
Thermal pad Die Pad P Solder the thermal pad on the bottom of the QFN package to the GND plane of the PCB. It is required for mechanical stability and will enhance thermal performance.