SLOU565 August   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Getting Started
      1. 2.1.1 Power Supplies
      2. 2.1.2 Input
      3. 2.1.3 Output
    2. 2.2 Application Circuit
      1. 2.2.1 Astable Mode
    3. 2.3 Evaluation Module Limitations
    4. 2.4 Electrostatic Discharge Caution
  8. 3Hardware Design Files
    1. 3.1 Schematic
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  9. 4Additional Information
    1. 4.1 Trademarks
  10. 5Related Documentation

2.2 Application Circuit

The TLC3555EVM can be configured in standard timer circuit configurations for evaluation. For typical applications, see the TLC3555-Q1 data sheet. Figure 3-1 shows the full schematic of the EVM. The EVM is populated with components for evaluation of the TLC3555-Q1. Resistors R5, R6, R8, and R9 are populated on pertinent pins providing flexibility for configuration of various application circuits. The EVM provides a copy of the TLC3555EVM circuitry for evaluation of timers in the SOIC package.