SLOU569 November   2023

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Setup
      1. 2.1.1 I2C Device Addresses
    2. 2.2 Header & Jumper Information
    3. 2.3 Test Points
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layout
    3. 3.3 Bill of Materials
  10. 4Additional Information
    1. 4.1 Trademarks

2.2 Header & Jumper Information

Table 2-3 TAS5827 Circuit Jumpers
DesignatorNamePositionsDescription
J3DVDD1

IN: Default, IOVDD supplies DVDD

OUT: DVDD disconnected

Drives the digital power supply for the TAS5827. If DVDD current draw wants to be measured need to externally drive DVDD to pin 2
J4GVDDN/AGate drive internal regulator output
J5AVDDN/AInternally regulated 5-V analog supply voltage
J8ADR/HW

1-2: Hardware Mode

2-3: Default, I2C Mode with 0xC0 as address

When shorted, DVDD puts the TAS5827 into Hardware Mode which also changes other pin functionality in the device. In Software mode, depending on the resistance value and connection changes the I2C Peripheral address
J9PD_DET-PDN

IN: Connects PDN and PD_DET, for use only in Hardware Mode

OUT: Default

This connection is for use in Hardware mode, which shorts PDN and PD_DET pin to turn off the device when the PVDD drops below 8 V
J10SDA/HW_SEL1

1-2: Default

2-3: Hardware Mode

Default configuration has pull-up for the I2C SDA. In Hardware mode, controls PWM Switching Frequency and Spread Spectrum Enable/Disable selection
J11SCL/HW_SEL0

1-2: Default

2-3:Hardware Mode

Default configuration has pull-up for the I2C SCL. In Hardware mode controls Analog gain and BTL/PBTL mode selection
J32VR_DIGN/AInternally regulated 1.5-V digital supply voltage. Dependent on DVDD
Table 2-4 J10: Hardware Control - HW_SEL1 Pin6
R10(GND)R8(DVDD)FSW&Class D Loop BandwidthCycle By Cycle Current Limit ThresholdSpread SpectrumModulation
0 ΩDNP768 kHz FSW, 175 kHz BWCBC Threshold = 80% OCPDisable1SPW
1 kΩDNP768 kHz FSW, 175 kHz BWCBC DisableDisable1SPW
4.7 kΩDNP768 kHz FSW, 175 kHz BWCBC Threshold = 40% OCPDisable1SPW
15 kΩDNP768 kHz FSW, 175 kHz BWCBC Threshold = 60% OCPDisable1SPW
DNP33 kΩ480 kHz FSW, 100 kHz BWCBC DisableEnableBD
DNP6.8 kΩ480 kHz FSW, 100 kHz BWCBC Threshold = 80% OCPEnableBD
DNP1.5 kΩ480 kHz FSW, 100 kHz BWCBC Threshold = 40% OCPEnableBD
DNP0 Ω480 kHz FSW, 100 kHz BWCBC Threshold = 60% OCPEnableBD
Table 2-5 J11: Hardware Control - HW_SEL0 Pin5
R11 (GND)R9 (DVDD)Analog GainH-Bridge Output Configuration
0 ΩDNP29.5 VP/FSBTL
1 kΩDNP20.9 VP/FSBTL
4.7 kΩDNP14.7 VP/FSBTL
15 kΩDNP7.4 VP/FSBTL
DNP33 kΩ7.4 VP/FSPBTL
DNP6.8 kΩ14.7 VP/FSPBTL
DNP1.5 kΩ20.9 VP/FSPBTL
DNP0 Ω29.5 VP/FSPBTL
Table 2-6 XMOS Circuit Jumpers
DesignatorNamePositionDescription
J22SCL

1-2: Default, PPC3 drives XMOS I2C bus to the TAS5827

OUT: Use Pin 1 and 3 to drive SCL externally to the TAS5827 on the EVM

The SCL Jumper offers a few options to provide or receive I2C signals. Default configuration connects the XMOS I2C bus to the TAS5827 to configure the device with PPC3. Disconnecting the jumper allows for the XMOS I2C bus to be connected to an external TAS5827 system board to configure that device with PPC3 using pins 2 and 3. Alternatively can use an external I2C bus to drive the TAS5827 on the EVM using pins 1 and 3.
J23SDA

1-2: Default, PPC3 drives XMOS I2C bus to TAS5827

OUT: Use Pin 1 and 3 to drive SDA externally to the TAS5827 on the EVM

The SDA Jumper offers a few options to provide or receive I2C signals. Default configuration connects the XMOS I2C bus to the TAS5827 to configure the device with PPC3. Disconnecting the jumper allows for the XMOS I2C bus to be connected to an external TAS5827 system board to configure that device with PPC3 using pins 2 and 3. Alternatively can use an external I2C bus to drive the TAS5827 on the EVM using pins 1 and 3.
Table 2-7 Audio Input IO Circuit Jumpers & Switches
DesignatorNamePositionsDescription
J26IOVDD

1-2: 1.8V IOVDD

2-3: Default, 3.3V IOVDD

Sets the IOVDD voltage for the Digital Interfaces
J27SCLK

1-2: Default, Bypass mode that sends SPDIF/XMOS I2S input to the TAS5827

2-3: Connect external PSIA connector to Pin 2-3 to drive input to TAS5827

Sets the SCLK input to be driven internally using USB/Optical input or driven externally with a PSIA connector
J28LRCLK

1-2: Default, Bypass mode that sends SPDIF/XMOS I2S input to the TAS5827

2-3: Connect external PSIA connector to Pin 2-3 to drive input to TAS5827

Sets the LRCLK input to be driven internally using USB/Optical input or driven externally with a PSIA connector
J29SDIN

1-2: Default, Bypass mode that sends SPDIF/XMOS I2S input to the TAS5827

2-3: Connect external PSIA connector to Pin 2-3 to drive input to TAS5827

Sets the SDIN input to be driven internally using USB/Optical input or driven externally with a PSIA connector
J31GPIO1 SEL

1-2: Default, sends the SDOUT data to the XMOS

2-3: Sends SDOUT Data to SPIDIF Optical Output

If the device is not using the Class-H feature, then this jumper can be using to sent the output I2S/TDM data to an external source of either the XMOS & USB or the optical output
Table 2-8 Power Supply Circuit Jumpers
DesignatorNamePositionsDescription
J15Ext_BST

IN: Default, TAS5827 Class H PWM output drives the LM5155 Boost voltage through the Feedback Pin

OUT: Disconnect Class H PWM signal

This jumper is used to connect the LM5155 Feedback Pin to the voltage generated by the Class H PWM Control Signal of the TAS5827
J16BST_Bypass

IN: Max BST Output

OUT: Default

When the device is using Class-H, shorting the BST Bypass jumper sets the LM5155 Boost to the max Boost Output
J195 VOUT: Connections for external 5 V and GND connectionIf the USB Power that drives the 5V rail is disconnected, this can be driven externally using this header
J213.3VN/A

The 3.3V rail used to power various components on the EVM. R33 can be removed and the 3.3V driven externally to analyze current draw of this rail.

Table 2-9 J33: IO-EXT Pin Description
NumberNameDescription
All odd pins (1 to 27)GNDGround connection
2,4,6,26N/AUnused floating pins
8AMP_SCLI2C serial control clock input for the TAS5827
10AMP_SDAI2C serial control clock input for the TAS5827
12LRCLKI2S/TDM Frame Clock
14SCLKI2S/TDM Bit Clock
16SDINI2S/TDM Data
20GPIO_FAULTGeneral-purpose input/output configured to be the active-low Fault pin
22GPIO1_Hybrid_ProGeneral-purpose input/output configured to be the Class-H PWM control pin
24GPIO2_WARNGeneral-purpose input/output configured to be the active-low warning pin
26PDNPower down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
28IOVDDThe 3.3V or 1.8V digital power supply