CSD18537NQ5A 60-V N-Channel NexFET Power MOSFETs
- SLPS391B June 2013 – July 2014 CSD18537NQ5A
  
  PRODUCTION DATA.

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DATA SHEET

CSD18537NQ5A 60-V N-Channel NexFET Power MOSFETs

1 Features

Ultra-Low Q_g and Q_gd
Low Thermal Resistance
Avalanche Rated
Pb Free Terminal Plating
RoHS Compliant
Halogen Free
SON 5 mm × 6 mm Plastic Package

2 Applications

High-Side Synchronous Buck Converter
Motor Control

3 Description

This 10 mΩ, 60 V, SON 5 mm x 6 mm NexFET™power MOSFET is designed to minimize losses in power conversion applications.

Top View

Product Summary

T_A = 25°C		TYPICAL VALUE		UNIT
V_DS	Drain-to-Source Voltage	60		V
Q_g	Gate Charge Total (10 V)	14		nC
Q_gd	Gate Charge Gate-to-Drain	2.3		nC
R_DS(on)	Drain-to-Source On Resistance	V_GS = 6 V	13	mΩ
R_DS(on)	Drain-to-Source On Resistance	V_GS = 10 V	10	mΩ
V_GS(th)	Threshold Voltage	3		V

Ordering Information⁽¹⁾

Device	Qty	Media	Package	Ship
CSD18537NQ5A	2500	13-Inch Reel	SON 5 x 6 mm Plastic Package	Tape and Reel
CSD18537NQ5AT	250	7-Inch Reel	SON 5 x 6 mm Plastic Package	Tape and Reel

For all available packages, see the orderable addendum at the end of the data sheet.

Absolute Maximum Ratings

T_A = 25°C		VALUE	UNIT
V_DS	Drain-to-Source Voltage	60	V
V_GS	Gate-to-Source Voltage	±20	V
I_D	Continuous Drain Current (Package limited)	50	A
	Continuous Drain Current (Silicon limited), T_C = 25°C	54
	Continuous Drain Current⁽¹⁾	11
I_DM	Pulsed Drain Current⁽²⁾	151	A
P_D	Power Dissipation⁽¹⁾	3.2	W
P_D	Power Dissipation, T_C = 25°C	75	W
T_J, T_stg	Operating Junction and Storage Temperature Range	–55 to 150	°C
E_AS	Avalanche Energy, single pulse I_D = 33 A, L = 0.1 mH, R_G = 25 Ω	55	mJ

Typical R_θJA = 40°C/W on a 1-inch², 2-oz. Cu pad on a
0.06-inch thick FR4 PCB.
Max R_θJC = 2.1°C/W, pulse duration ≤100 µs, duty cycle
≤1%

R_DS(on) vs V_GS

Gate Charge

4 Revision History

Changes from A Revision (February 2014) to B Revision

Reduced silicon current limit to 54 A due to increase in R_θJCGo
Increased pulsed current limit to 151 Go
Added line for maximum power dissipation with case temperature held to 25ºC Go
Updated the pulsed current conditions Go
Increased the maximum R_θJC to 2.1 ºC/W Go
Updated Figure 1 from a normalized R_θJA curve to an R_θJC curveGo
Updated Figure 10 to show an improved SOAGo
Updated Figure 12 to show a 50-A package current limit Go

Changes from * Revision (June 2013) to A Revision

Added part number to titleGo
Added more information to descriptionGo
Updated ordering information to include small reel informationGo
Removed T_C = 25°C condition from package limited continuous drain currentGo

5 Specifications

5.1 Electrical Characteristics

(T_A = 25°C unless otherwise stated)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
STATIC CHARACTERISTICS
BV_DSS	Drain-to-Source Voltage	V_GS = 0 V, I_D = 250 μA	60			V
I_DSS	Drain-to-Source Leakage Current	V_GS = 0 V, V_DS = 48 V			1	μA
I_GSS	Gate-to-Source Leakage Current	V_DS = 0 V, V_GS = 20 V			100	nA
V_GS(th)	Gate-to-Source Threshold Voltage	V_DS = V_GS, I_D = 250 μA	2.6	3	3.5	V
R_DS(on)	Drain-to-Source On Resistance	V_GS = 6 V, I_D = 12 A		13	17	mΩ
R_DS(on)	Drain-to-Source On Resistance	V_GS = 10 V, I_D = 12 A		10	13	mΩ
g_ƒs	Transconductance	V_DS = 30 V, I_D = 12 A		62		S
DYNAMIC CHARACTERISTICS
C_iss	Input Capacitance	V_GS = 0 V, V_DS = 30 V, ƒ = 1 MHz		1140	1480	pF
C_oss	Output Capacitance			136	177	pF
C_rss	Reverse Transfer Capacitance			4	5.2	pF
R_G	Series Gate Resistance			5.5	11	Ω
Q_g	Gate Charge Total (10 V)	V_DS = 30 V, I_D = 12 A		14	18	nC
Q_gd	Gate Charge Gate-to-Drain			2.3		nC
Q_gs	Gate Charge Gate-to-Source			4.7		nC
Q_g(th)	Gate Charge at V_th			3.3		nC
Q_oss	Output Charge	V_DS = 30 V, V_GS = 0 V		25		nC
t_d(on)	Turn On Delay Time	V_DS = 30 V, V_GS = 10 V, I_DS = 12 A, R_G = 0 Ω		5.8		ns
t_r	Rise Time			4		ns
t_d(off)	Turn Off Delay Time			14.4		ns
t_ƒ	Fall Time			3.2		ns
DIODE CHARACTERISTICS
V_SD	Diode Forward Voltage	I_SD = 12 A, V_GS = 0 V		0.8	1	V
Q_rr	Reverse Recovery Charge	V_DS= 30 V, I_F = 12 A, di/dt = 300 A/μs		54		nC
t_rr	Reverse Recovery Time	V_DS= 30 V, I_F = 12 A, di/dt = 300 A/μs		40		ns

5.2 Thermal Information

(T_A = 25°C unless otherwise stated)

THERMAL METRIC		MIN	TYP	MAX	UNIT
R_θJC	Junction-to-Case Thermal Resistance ⁽¹⁾			2.1	°C/W
R_θJA	Junction-to-Ambient Thermal Resistance ⁽¹⁾⁽²⁾			50	°C/W

(1) R_θJC is determined with the device mounted on a 1-inch² (6.45-cm²), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches
(3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. R_θJC is specified by design, whereas R_θJA is determined by the user’s board design.

(2) Device mounted on FR4 material with 1-inch² (6.45-cm²), 2-oz. (0.071-mm thick) Cu.

Max R_θJA = 50°C/W when mounted on 1 inch² (6.45 cm²) of
2-oz. (0.071-mm thick) Cu.

Max R_θJA = 125°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu.

5.3 Typical MOSFET Characteristics

(T_A = 25°C unless otherwise stated)

Figure 1. Transient Thermal Impedance

Figure 2. Saturation Characteristics

Figure 4. Gate Charge

Figure 6. Threshold Voltage vs Temperature

Figure 8. Normalized On-State Resistance vs Temperature

Figure 10. Maximum Safe Operating Area

Figure 12. Maximum Drain Current vs Temperature

Figure 3. Transfer Characteristics

Figure 5. Capacitance

Figure 7. On-State Resistance vs Gate-to-Source Voltage

Figure 9. Typical Diode Forward Voltage

Figure 11. Single Pulse Unclamped Inductive Switching

6 Device and Documentation Support

6.1 Trademarks

NexFET is a trademark of Texas Instruments.

6.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

6.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.