SLUA560D June   2011  – March 2022 UCC28950 , UCC28950-Q1 , UCC28951 , UCC28951-Q1

 

  1.   Trademarks
  2. 1 Design Specifications
  3. 2 Functional Schematic
  4. 3 Power Budget
  5. 4 Transformer Calculations (T1)
  6. 5 QA, QB, QC, QD FET Selection
  7. 6 Selecting LS
  8. 7 Output Inductor Selection (LOUT)
  9. 8 Output Capacitance (COUT)
  10. 9 Select FETs QE and QF
  11. 10Input Capacitance (CIN)
  12. 11Setting Up the Current Sense (CS) Network (CT, RS, RRE, DA)
  13. 12Voltage Loop and Slope Compensation
  14. 13Setting Turn-on Delays to Achieve Zero Voltage Switching (ZVS)
  15. 14Turning SR FETs-off Under Light Load Conditions
  16. 15600 W FSFB Detailed Schematic and Test Data
  17. 16References
  18. 17Revision History

6 Selecting LS

Calculating the shim inductor (LS) is based on the amount of energy required to achieve zero voltage switching. This inductor needs to able to deplete the energy from the parasitic capacitance at the switch node. The following equation selects LS to achieve Zero Voltage Switching (ZVS) at 100% load down to 50% load based on the primary FET’s average total COSS at the switch node.

Note:

There might be more parasitic capacitance than was estimated at the switch node and LS might have to be adjusted based on the actual parasitic capacitance in the final design.

Equation 40. L S ≥ 2 × C O S S _ Q A _ ⁡ A V G V I N M A X 2 I P P 2 - Δ I L O U T 2 × a 1 2 - L L K ≈ 26   u H

For this design Vitec Electronics Corporation designed a customer LS, part number 60PR964. 60PR964 had a DC resistance (DCRLS) of 27 mΩ.

Equation 41. D C R L S = 27   m Ω

Estimate LS power loss (PLS) and readjust remaining power budget:

Equation 42. P L S = 2 × I P R M S 2 × D C R L S ≈ 0.5   W
Equation 43. P B U D G E T = P B U D G E T - P L S ≈ 29.2   W