SLUA560D June 2011 – March 2022 UCC28950 , UCC28950-Q1 , UCC28951 , UCC28951-Q1
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Description | Min | Typ | Max |
---|---|---|---|
Input Voltage | 370 V (VINMIN) | 390 V (VIN) | 410 V (VINMAX) |
Output Voltage (VOUT) | 11.4 V | 12 V (VOUT) | 50 V |
Continuous Output Power (POUT) | 600 W | ||
Allowable VOUT Transient | 600 mV ( VTRAN) | ||
Full Load Efficiency | 93% (η) | 94% | |
Inductor (LOUT) Switching Frequency | 200 kHz (fS) |
To reach the efficiency goal in this PSFB design, careful consideration needs to be taken in selecting electrical components. The devices need to be selected based voltage rating, current rating and power dissipation. The initial step in this design process is to set a power budget (PBUDGET) which the total losses of the electrical components selected for the design cannot exceed.
The PSFB uses a transformer to deliver energy from the primary to the secondary. The voltage is stepped up or down through the transformers turns ratio (a1).
Estimated FET voltage drop (VRDSON):
Select transformer turns based on 70% duty cycle (DMAX) at minimum specified input voltage. This will give some room for dropout if a PFC front end is used.
Calculated typical duty cycle (DTYP) based on average input voltage.
To keep the RMS current in the output capacitance to a minimum LOUT will be selected so the inductor ripple current (ΔILOUT) will be 20% of the DC output current. ΔILOUT is needed to calculate transformer peak and RMS currents
Care needs to be taken in selecting a transformer with the correct amount of magnetizing inductance (LMAG). The following equations calculate the minimum magnetizing inductance of the primary of the transformer (T1) to ensure the converter operates in peak-current mode control. If LMAG is too small the magnetizing current could cause the converter to operate in voltage mode control instead of peak-current mode control. This is because the magnetizing current is too large, it will act as a PWM ramp swamping out the current sense signal across RS.
Figure 4-1 shows T1 primary current (IPRIMARY) and synchronous rectifiers currents, (QE (IQE) and QF (IQF)), with respect to the synchronous rectifier gate drive currents. Note that IQE and IQF are also T1’s secondary winding currents as well. Variable D is the converters duty cycle.
Calculate T1 secondary RMS current (ISRMS):
Secondary RMS current (ISRMS1) when energy is being delivered to the secondary:
Secondary RMS current (ISRMS2) when current is circulating through the transformer when QE and QF are both on.
Secondary RMS current (ISRMS3) caused by the negative current in the opposing winding during freewheeling period, please refer to Figure 4-1.
Total secondary RMS current (ISRMS):
Calculate T1 Primary RMS Current (IPRMS):
T1 Primary RMS (IPRMS1) current when energy is being delivered to the secondary.
T1 Primary RMS (IPRMS2) current when the converter is free wheeling.
Total T1 primary RMS current (IPRMS)
The transformer calculations were given to Vitec a magnetic manufacturer to design a custom transformer to meet our design requirements. The transformer they designed for this application is part number 75PR8107 and the transformer has the following specifications.
Measured leakage inductance on the Primary:
Transformer Primary DC resistance:
Transformer Secondary DC resistance:
Estimated transform losses (PT1) are twice the copper loss.
This is just an estimate and the total losses can vary based on magnetic design.
Calculate remaining power budget:
The FETs to drive the HBridge (QA..QD) need to selected based on maximum drain to source voltage (VdsQA_max) and peak drain to source current (IdsQA_max).
The FETs then need to be selected based on efficiency goals and FET power dissipation (PQA) and is a trial an error process. Equations 32 through 38 are used to estimate PQA based on FET data sheet parameters. To meet our efficiency goals, we selected a 20 A, 650 V, CoolMOS FETs from Infineon that had an estimated PQA of 2.1 W and would enable us to hit our efficiency goals.
In this design, to meet efficiency and voltage requirements 20 A, 650 V, CoolMOS FETs from Infineon were chosen for QA..QD.
FET drain to source on resistance:
FET Specified COSS:
Voltage across drain-to-source (VdsQA) where COSS was measured, data sheet parameter:
Calculate average Coss [2]:
QA FET gate charge:
Voltage applied to FET gate to activate FET:
Calculate QA losses (PQA) based on Rds(on)QA and gate charge (QAg):
Recalculate power budget:
Calculating the shim inductor (LS) is based on the amount of energy required to achieve zero voltage switching. This inductor needs to able to deplete the energy from the parasitic capacitance at the switch node. The following equation selects LS to achieve Zero Voltage Switching (ZVS) at 100% load down to 50% load based on the primary FET’s average total COSS at the switch node.
There might be more parasitic capacitance than was estimated at the switch node and LS might have to be adjusted based on the actual parasitic capacitance in the final design.
For this design Vitec Electronics Corporation designed a customer LS, part number 60PR964. 60PR964 had a DC resistance (DCRLS) of 27 mΩ.
Estimate LS power loss (PLS) and readjust remaining power budget:
To keep the RMS current in the output capacitance to a minimum LOUT will be designed for and inductor ripple current (∆ILOUT) will be 20% of the DC output current.
Calculate output inductor RMS current (ILOUT_RMS):
The LOUT inductor requirements to meet these design specifications was given to Vitec Electronics Corp and they design a custom inductor for this design that met are design requirements, part number 75PR108. The 75PR108 had a DC resistance (DCRLOUT) of 750 µΩ
Estimate output inductor losses (PLOUT) and recalculate power budget. Note PLOUT is an estimate of the inductor losses and was estimated to twice the copper loss. Note this may vary based on magnetic manufactures. It is advisable to double check the magnetic loss with the magnetic manufacture.