Developed for high-voltage applications where isolation and reliability is required, the UCC21520 delivers reinforced isolation of 5.7 kVRMS along with a common mode transient immunity (CMTI) greater than 100 V/ns, and it has the industry’s best-in-class propagation delay of 19 ns and the best channel-to-channel delay matching of less than 5 ns which enables high switching frequency, high-power density and efficiency. In this application report, design considerations and benefits of the UCC21520’s fast dynamic response are introduced with discussion of its wide application in a great variety of power electronics topologies.
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To fully enhance the performance of the latest high-voltage power semiconductors, such as super junction MOSFETs, trench/field stop IGBTs, wide band-gap SiC and GaN transistors, a universal gate driver becomes a critical interface which not only supports enough peak source/sink current, but also facilitates fast dynamic response with robustness and protection for higher switching frequency and higher efficiency applications.
The flexible, universal capability of the UCC21520 with up to 18-V VCCI and 25-V VDDA/VDDB allows the device to be used as a low-side, high-side, high-side/low-side or half-bridge driver with MOSFETs, IGBTs or SiC MOSFETs. With its integrated components, advanced protection features (UVLO, deadtime and disable) and the optimized dynamic performances, the UCC21520 enables designers to build smaller, more robust designs for enterprise, telecom, automotive and industrial applications allowing for faster time to market.
The two output buffer stages of UCC21520 provides 4-A source and 6-A sink current, which provides satisfied rising and falling time (<30 ns) with load capacitance up to 10 nF. However, in some scenarios where the load is larger than 10 nF, external totem-pole buffer stage with discrete transistor should be applied for achieving required rising and falling switching time. Figure 1 shows the UCC21520 drives 30 nF with single channel (green), and the rising time is 110 ns from 5 V to 20 V on the output waveform, which is too long and does increase the switching loss. UCC21520 has two identical designed channels with both propagation delay matching and pulse width distortion less than 5 ns, which make it possible to parallel the output channel and double the gate drive strength. This application note will investigate the dynamic performance of the UCC21520, and also discusses feasibility of paralleling UCC21520 two output channels.
The propagation delay mismatch will introduce internal shoot-through if the two output channels are paralleled. Figure 2 shows the simplified circuit diagram with UCC21520 two output channels in parallel driving a heavy load. In this example, it is assumed that the channel A turn-on happens earlier than channel B, or channel A turn-off later than channel B. The red dotted line shows the shoot-through path which shorts VDD to ground with very small impedance, which is typically 1.5 Ω combining pull-up and pull-down resistance. Therefore, there will be large current flow through the gate driver device, and will result in additional internal heat. The estimated loss per cycle can be calculated by:
where
To make sure UCC21520 two channels can be used in parallel, it is essential to quantify the delay matching data at different VDD voltage and temperature.
To evaluate the dynamic characteristics of the UCC21520, propagation delay, propagation delay matching and pulse width distortion performance are tested through different VDD voltage and temperature corners. For definition of these parameters, please refer to UCC21520 datasheet.
Figure 3 and Figure 4 show the propagation delay measurement data with temperature and VDD voltage corners. It can be seen that the propagation delay is independent of VDD voltage, and the typical propagation delay is less than 20 ns across wide temperature range, which helps to improve system response for high frequency applications, for example, timing control of zero voltage switching (ZVS), fast response for system protection, etc.
Figure 5 and Figure 6 show the propagation delay matching measurement data at temperature and VDD voltage corners. It can be seen that the delay matching at both the rising and falling edges is less than 2 ns within wide temperature and VDD ranges, which does help the channel parallel performance to drive large capacitance load.
Figure 7 and Figure 8 shows the pulse width distortion (PWD) measurement data, and it is less than 1 ns through all the temperature and VDD voltage corners. Low PWD does help deliver the correct and precise response with the given input signal, and maintain stable system operation.
In summary, low propagation delay, low propagation delay matching and low pulse width distortion does position the UCC21520 as the best-in-class gate driver with the best-in-class dynamic response. It is important to note that less than 2-ns propagation delay matching help to parallel the two output channels, double the gate drive strength and increase the versatility of the UCC21520 for a variety of applications.