The following instructions are useful when constructing any stacking configuration with the BQ77915. Many steps refer to the pin connections that can best be understood by observing the schematic. Further information on the setup of the Stacking Implementations is found in the bq77915 3-5S Low Power Protector with Cell Balancing and Hibernate Mode data sheet.
Ensure each device has a connection on at least the three lowest cell inputs.
Ensure that the CCFG pin of each device is configured appropriately for the specific number of cells, either three, four, or five.
Connect the CHG pin of the upper device with a RCTRC to the CTRC pin of the immediate lower device.
Connect the DSG pin of the upper device with a RCTRD to the CTRD pin of the immediate lower device.
All upper devices must have the SRP and SRN pins shorted to the VSS pin.
Connect the upper CBI pins with RCB to the CBO pin of the immediate lower device.
Connect upper LPWR pins with an RHIBto the PRES pin of the immediate lower device.
Connect the upper OCDP pins with a 10-MΩ resistor to VSS. Use the lower OCDP pin to program the OCD1/2 delay.
Figure 1-2 Top Device with HIBERNATE Mode Enabled
Figure 1-3 Middle Device(s) with HIBERNATE Mode Enabled
Figure 1-4 Bottom Device with HIBERNATE Mode Enabled