The Active Miller clamp (CLAMP) is used to prevent the power transistor from false turn-on due to Miller capacitance-induced current. The active Miller clamp adds a low impedance path between power transistor gate terminal and VEE2 to pull the gate of the external FET hard to VEE2, bypassing any external gate resistors. The Miller clamp engages when the OUTH pin falls below V_CLPTH, which is the threshold voltage that can be selected using SPI programming. The integrated internal Miller Clamp is shown in Figure 3-25. The CLAMP pin can also be configured to drive an external Miller Clamp FET if more pull-down strength is required, as shown in Figure 3-26. The external Miller Clamp FET also provides the ability to optimize placement of the clamp such that it is very close to the gate of the power transistor. Both options can be easily tested by configuring the output using SPI and making minor changes to the layout.

Figure 3-25 Integrated Internal Miller Clamp

Figure 3-26 Integrated Driver for External Miller Clamp