SLUAA16A August   2020  – October 2023 BQ79600-Q1

 

  1.   1
  2.   BQ79600-Q1 Design Recommendations
  3.   Trademarks
  4. 1Circuit Design
    1. 1.1 Power Supply (BAT, CVDD, DVDD, VIO pins)
    2. 1.2 Inhibit Output (INH pin)
    3. 1.3 Communication to Host (MOSI/RX, MISO/TX, nCS, SCLK, nUART/SPI (SPI_RDY) pins)
    4. 1.4 Fault Output (NFAULT pin)
    5. 1.5 Communication to Battery Monitor Device (COMHP, COMHN, COMLP, COMLN pins)
  5. 2Layout Guidelines
    1. 2.1 Ground Planes
    2. 2.2 Bypass Capacitors for Power Supplies and References
    3. 2.3 UART/SPI Communication
    4. 2.4 Daisy Chain Communication
  6. 3Daisy Chain Signal Integrity
    1. 3.1 Daisy Chain Receiver Threshold
    2. 3.2 Common and Differential Mode Noise
    3. 3.3 BCI Performance
    4. 3.4 Radiated Emissions Performance
  7. 4Summary
  8. 5References
  9. 6Revision History

1.2 Inhibit Output (INH pin)

INH pin is a PMOS open drain output used to control the external voltage regulators such as a PMIC when reverse wakeup feature is used. This pin needs a 100 KΩ pull-down resistor to GND for correct functionality. If reverse wakeup feature is not used, connect INH directly to BAT pin.

Table 1-2 INH Design Considerations
Pin Purpose Reverse Wakeup Used Reverse Wakeup Not Used
INH PMOS open drain output to control system voltage regulators. Connect a 100 KΩ resistor to GND. Connect this pin to BAT pin. Don't leave floating.