SLUAA16A August   2020  – October 2023 BQ79600-Q1

 

  1.   1
  2.   BQ79600-Q1 Design Recommendations
  3.   Trademarks
  4. 1Circuit Design
    1. 1.1 Power Supply (BAT, CVDD, DVDD, VIO pins)
    2. 1.2 Inhibit Output (INH pin)
    3. 1.3 Communication to Host (MOSI/RX, MISO/TX, nCS, SCLK, nUART/SPI (SPI_RDY) pins)
    4. 1.4 Fault Output (NFAULT pin)
    5. 1.5 Communication to Battery Monitor Device (COMHP, COMHN, COMLP, COMLN pins)
  5. 2Layout Guidelines
    1. 2.1 Ground Planes
    2. 2.2 Bypass Capacitors for Power Supplies and References
    3. 2.3 UART/SPI Communication
    4. 2.4 Daisy Chain Communication
  6. 3Daisy Chain Signal Integrity
    1. 3.1 Daisy Chain Receiver Threshold
    2. 3.2 Common and Differential Mode Noise
    3. 3.3 BCI Performance
    4. 3.4 Radiated Emissions Performance
  7. 4Summary
  8. 5References
  9. 6Revision History

1.1 Power Supply (BAT, CVDD, DVDD, VIO pins)

BAT, CVDD, DVDD and VIO pins are supplies in BQ79600-Q1 used to provide power to different blocks in the chip.

BAT pin is the battery supply input which supplies the internal LDOs and wakeup circuit. When reverse wakeup feature is used, this pin should be connected to a 12 V battery through a 10 Ω resistor and bypassed to GND with a 0.1 µF/50 V capacitor, placing capacitor as close as possible to the pin. Battery voltage can be as low as 5.5 V and as high as 24 V. If reverse wakeup feature is not used, this pin can be connected to a regulated 5 V supply from the SBC/PMIC in the system with as low as 4.75 V and as high as 5.25 V.

CVDD pin is a dedicated 5 V supply for the vertical interface. This voltage is generated internally by the BQ79600-Q1 device. This pin needs to be decoupled with a 0.22 µF/10 V capacitor to GND for correct operation. Place capacitor as close as possible to CVDD pin and don't connect any external load to this pin. If reverse wakeup feature is not used and BAT pin is powered from a regulated 5V supply, connect CVDD directly to BAT pin and still connect the 0.22 µF/10 V decoupling capacitor.

DVDD pin is a 1.8 V regulated output to supply the internal digital circuits and it is generated internally by the BQ79600-Q1 device from the CVDD 5 V supply. It needs to be decoupled with a 0.22 µF/10 V capacitor to GND for correct operation. Place capacitor as close as possible to DVDD pin and don't connect any external load to this pin.

VIO pin is the power supply input for the UART and SPI I/O pins. This pin should be connected to an external regulated supply, typically 3.3 V or 5 V. The microcontroller voltage reference for UART or SPI I/O pins should be the same as the voltage reference used for VIO. In a typical application, this regulated voltage is generated by a PMIC in the system and is connected to both the BQ79600-Q1 VIO pin and the power supply pin for UART or SPI I/Os in the microcontroller. Decouple with a 0.1 µF/10 V capacitor to GND and place capacitor as close as possible to VIO pin. VIO should be powered before SCLK, nCS, RX/MOSI, TX/MISO, NFAULT, nUART/SPI (SPI_RDY) are driven.

Figure 1-1 shows the recommended power supply circuit design when a 12 V battery is directly used to power the BQ79600-Q1 and reverse wakeup feature is used. Figure 1-2 shows the recommended power supply circuit design when a regulated 5 V supply is used to power the BQ79600-Q1 and reverse wakeup feature is not used.

GUID-20200820-CA0I-NNLZ-TV6R-TLDJFNJHJGQ1-low.png Figure 1-1 12 V Battery and Automatic Host Wakeup
GUID-20200820-CA0I-2NH3-4G49-QQ2NWSVF2QJV-low.png Figure 1-2 5 V Regulated Supply and No Automatic Host Wakeup
Table 1-1 Power Supply Design Considerations
Pin Purpose Reverse Wakeup Used Reverse Wakeup Not Used
BAT Supplies internal LDOs and wakeup circuit. Connect to external 12 V battery through 10 Ω resistor and bypass to GND with 0.1 µF/50 V. Connect to external 12 V battery through 10 Ω resistor and bypass to GND with 0.1 µF/50 V, or connect to regulated 5 V supply and short to CVDD.
CVDD 5 V supply for daisy chain communications. Decouple with 0.22 µF/10 V to GND. Decouple with 0.22 µF/10 V to GND. If BAT powered with 5 V supply, connect this pin to BAT pin.
DVDD 1.8 V supply for internal digital circuits. Bypass with 0.22 µF/10 V capacitor to GND.
VIO 3.3 V or 5 V supply input for UART/SPI input/output pins. Decouple with a 0.1 µF/10 V capacitor to GND.