SLUAA16A August   2020  – October 2023 BQ79600-Q1

 

  1.   1
  2.   BQ79600-Q1 Design Recommendations
  3.   Trademarks
  4. 1Circuit Design
    1. 1.1 Power Supply (BAT, CVDD, DVDD, VIO pins)
    2. 1.2 Inhibit Output (INH pin)
    3. 1.3 Communication to Host (MOSI/RX, MISO/TX, nCS, SCLK, nUART/SPI (SPI_RDY) pins)
    4. 1.4 Fault Output (NFAULT pin)
    5. 1.5 Communication to Battery Monitor Device (COMHP, COMHN, COMLP, COMLN pins)
  5. 2Layout Guidelines
    1. 2.1 Ground Planes
    2. 2.2 Bypass Capacitors for Power Supplies and References
    3. 2.3 UART/SPI Communication
    4. 2.4 Daisy Chain Communication
  6. 3Daisy Chain Signal Integrity
    1. 3.1 Daisy Chain Receiver Threshold
    2. 3.2 Common and Differential Mode Noise
    3. 3.3 BCI Performance
    4. 3.4 Radiated Emissions Performance
  7. 4Summary
  8. 5References
  9. 6Revision History

2.4 Daisy Chain Communication

It is important to have proper layout on the COMHP/N and COMLP/N circuits to have the best robust daisy chain communication.

Maintaining signal integrity on the daisy chain communication lines is critical to the success of this part.

  1. Keep differential traces as short as possible and as straight as possible. Minimize turns and avoid any looping on the traces.
  2. Keep the differential traces on the same layers. Run the trace in parallel with shielding and matching trace impedance.
  3. Place the isolation components close to the connectors.
  4. When using capacitive isolation, place the high voltage capacitor of the COMxP/N pair (where x = H, L) close to each other along the parallel traces.
  5. Create a keep-out area (no other traces and no ground plane) around the daisy chain components in all PCB layers.
GUID-20200805-CA0I-T7CL-S0B1-LMSNPNKFKJGX-low.png Figure 2-1 Daisy Chain Layout Considerations