SLUAA81A October   2020  – February 2022 BQ769142 , BQ76922 , BQ76942 , BQ76952

 

  1.   Trademarks
  2. 1Introduction
  3. 2Cell Balancing Circuit Considerations
    1. 2.1 Internal Cell-Balancing Circuit Design
    2. 2.2 External Cell-Balancing Circuit Design Using N-Channel FETs
    3. 2.3 External Cell-Balancing Circuit Design Using P-Channel FETs
    4. 2.4 External Cell-Balancing Circuit Design Using BJTs
    5. 2.5 Voltage Measurement Accuracy During Balance
  4. 3Stand-Alone Balancing Algorithm and Settings
  5. 4Considerations for a Host-Balancing Algorithm
  6. 5Timing Information
  7. 6Debugging Common Issues With Cell Balancing
    1. 6.1 Using a Resistor Divider as a Cell Simulator
  8. 7References
  9. 8Revision History

2 Cell Balancing Circuit Considerations

Cell balancing of a particular cell consists of enabling an integrated FET switch across the cell. The balancing current is determined by value of the input filter resistors selected when using internal balancing. FETs or BJTs can be used to increase the balance current in applications where the internal balancing current may not be sufficient. The next sections will discuss circuit design considerations for internal balancing, external balancing with N-channel FETs, external balancing with P-channel FETs, and external balancing with BJTs. Considerations for power dissipation and timing will also be discussed.