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The BQ769x2 family of battery monitor devices is designed with integrated high-side N-channel MOSFET drivers CHG and DSG. High-side switching allows easy interface to the battery with simple communication interfaces referenced to PACK- which can still operate when the battery is protected. The data sheet and evaluation module schematics and Figure 1-1 show FETs on the high-side current path. The BQ769x2 uses series FETs connected in a common drain configuration. The charge FET pulls the charger down to the battery voltage when on and the discharge FET pulls the load up to PACK+ when on. Low-side switching may be desired when the system specifications include an isolated interface, or require low side switching, or the design implements FETs not easily driven on the high side. Figure 1-2 shows FETs on the low side, again with a common drain configuration. The discharge FET pulls PACK- down to battery negative when on and the charge FET pulls the charger negative up to the battery negative voltage when on.
The BQ769x2 does not include integrated low-side drivers, but has digital outputs DDSG and DCHG which combine the FET output states with the precharge and predischarge states and can signal the desired state of the FETs. To implement a driver it is good to look at the voltage range needed for the FET gates. With the circuit "GND" reference at the battery negative, when the discharge FET is off the discharge FET gate is at GND and PACK- can be pulled to the PACK+ by a load resistance as shown in Figure 1-3. The system cannot charge in this state and the charge FET can be off with the gate voltage at VBAT also. When the discharge FET is turned on its gate voltage is raised to a voltage VFETON which will turn on the discharge FET. PACK- is pulled down toward the GND voltage as shown in Figure 1-4. The charge FET gate can also be turned on by the VFETON voltage to eliminate the voltage drop across the body diode and avoid heating the FET. Neglecting the voltage drop of the sense resistor and FET resistances PACK- voltage is at GND.
When the charge FET is off with a charger attached, the PACK- voltage is pushed below the GND level. For the charge FET to stay off the gate voltage must be near the PACK- voltage as shown in Figure 1-5. When the charge FET is on with the charger attached, the gate is raised to the VFETON voltage and PACK- is pulled up toward GND, see Figure 1-6.
If a reversed charger can be connected to the battery both the battery and charger want to push current in the same direction. Once the fault is detected and the FETs open, the reversed charger pushes the PACK- voltage above the PACK+ voltage. The discharge FET must withstand the high voltage, and the charge FET gate voltage must rise to prevent damage to the FET. This condition is shown in Figure 1-7.
Figure 1-8 summarizes the voltage range of the FET gates. The discharge gate must move from VFETON when on to GND when off. The charge FET gate voltage must move from VFETON to the PACK- voltage to turn the FET off, but depending on the FET and system conditions that voltage may have a large range above or below the battery voltage. A driver circuit design will need to provide and accommodate these voltage ranges.
A FET driver circuit then will need to take the digital control signal from the BQ769x2, provide a supply voltage for the VFETON high level, and provide for switching the gates accommodating the voltage range in Figure 1-8 with a speed suitable for the system design.
Figure 2-1 shows a basic circuit approach where a regulator provides a VFETON voltage for a driver which provides level shifting of the digital signal from the BQ76952 to the VFETON voltage. The resistor R4 brings the drive voltage to the discharge FET gate. With the extra range of the charge FET gate, Q3 allows the gate voltage to go negative when the Cdrive is off. D1 blocks current into the driver when PACK- is high. D2 limits the gate -source voltage of the Q1 charge FET. R1 provides a current limit from the driver as Cdrive turns on if Q1 is slow to turn on. R2 turns off the FET when Cdrive goes low since D1 prevents the driver from pulling current from the gate.
When the driver can accept its output being pulled above the supply, a circuit such as Figure 2-2 might be used. D3 limits the voltage to the driver to its safe level and the gate-source voltage of Q3. R1 provides a limited current bypass past D1 so that the driver can help pull down the gate; it must limit the current back into D3 when PACK- is at its maximum voltage. So turn off will still be slow, and once Q1 begins to turn off and PACK- falls, it is R2 which completes turn off of the charge FET Q1. Since most IC drivers have an ABS MAX output of the driver voltage, a special driver is required for this type implementation.
Figure 2-3 shows a concept where the charge FET Q1 is driven on by the driver or is clamped off by Q4. This technique could be very effective at turning off Q1, but would require continuous current whether the charge FET was on or off.
Figure 2-4 is much like the simple driver circuit but with a gain circuit to help turn off the charge FET more quickly than with R2 alone. This circuit is powered by the Q1 gate voltage and Q4 will be on while voltage is present even as PACK- drops below GND. Either a PNP or P-channel FET could be used for Q4, the FET would be voltage controlled requiring less current, but VGSth may be larger than the VBE of the PNP transistor. The additional diode D3 keeps the base of Q4 above the emitter when the driver is on. The driver must provide current for both the RGS resistor R2 and the base resistor R5, so more current is required than the simple driver circuit while the FET is on.
A high performance option would be to use an isolated gate driver for the charge path as represented in Figure 2-5. The isolated driver would be very effective at driving the charge FET gate high or low as needed regardless of the PACK- voltage, but would require an isolated power supply.
Test circuits in this application report use the simple driver concept of Figure 2-1 and the PNP circuit of Figure 2-4.
Data memory configuration must be set to use low-side FETs with the BQ769x2 devices. By default the FET drivers are off in the data memory, but the charge pump is enabled. DDSG and DCHG are also disabled. The Settings:FET:FET Options[FET_CTRL_EN] bit is set by default and must remain set for the BQ769x2 to control DCHG and DDSG. Changes will include:
The following settings show an example of changes for basic low-level testing with 3.3-V REG1 and DCHG and DDSG high when on.
Settings:Configuration:REG12 Config 0x0D
Settings:Configuration:REG0 Config 0x01
Settings:Configuration:DCHG Pin Config 0xA2
Settings:Configuration:DDSG Pin Config 0xA2
Settings:FET:Chg Pump Control 0x00
Additional configuration for cells used and the desired device operation are needed. In testing for this application report additional changes were made for protection conditions. FETs were enabled as needed, SLEEP was generally disabled so the CHG would not switch with SLEEP.
An example circuit configuration for the BQ76952 is shown in Figure 3-1, this circuit is common for the driver options described in this application report. The charge pump is not used and CP1 is tied to BAT, so the BQ769x2 will draw the extra current noted in the data sheeet until the charge pump is disabled in the configuration. DSG and CHG are not used and are left open. PACK is pulled up with 10 kΩ. Both regulators are shown connected although only REG1 is used in testing. DDSG and DCHG are used for output and are not available for other functions. The schematic shows 16 cell support but should be configured for the cell count required. Testing for this application report was conducted at 40 V.