There are two basic operation modes, PWM mode and PFM mode, selectable by the mode detection block. The integrator in the voltage loop can improve output-voltage accuracy issues. The integrated oscillator generates the fixed clock. Implementing slope compensation in the modulator avoids subharmonic oscillation when the duty cycle is higher than 50% in PWM mode. The emulated ramp generator with the smart loop-bandwidth control circuit can adjust the DC gain to achieve high bandwidth over all output rails. And even though there is an integrator, unlike PCM control, the integrator in AECM control can improve output-voltage accuracy with no direct impact on loop response speed.

The PWM mode control scheme is similar to PCM control. As shown in Figure 2-2 on the following page, the internal clock initials one on-pulse; the high-side FET then turns on, with current increasing in the inductor. When the emulated ramp voltage, feedback voltage and slope compensation voltage reach the integrated reference voltage, the high-side FET turns off and the low-side FET turns on until the next clock cycle. Therefore, in PWM mode, the switching frequency is truly fixed.

AECM control implements PFM mode to achieve high efficiency under light loads. With a load current decrease, the device enters into discontinuous conduction mode (DCM) from continuous conduction mode (CCM). In both modes, the switching frequency is fixed; the width of the on-pulse (Ton) depends on the load current. Lighter loads have a shorter Ton. AECM has an on-time generator like the D-CAP2 control topology, but that generator is disabled in PWM mode. With the load current further decreasing, the Ton decreases down to the internal clamped on-time, while the AECM device steps into PFM mode with the internal clock blocked and the on-time generator enabled. As shown in Figure 2-2, the control scheme of PFM mode is similar to the D-CAP2 control scheme.