SLUAAG5 March 2022 TPS62933
Using the typical application as an example, Vin = 24 V, Vout = 5 V, Iout = 3 A, fsw = 500 kHz, L = 6.8 μH. For the voltage divider resistance, R1 = 52.5 kΩ and R2 = 10 kΩ.
With the method demonstrated in Part I, the calculated output capacitance upper limit is 106 μF without feedforward capacitor. Here 20 × C3216X5R1V226M160AC capacitors are selected for lower voltage ripple and better transient performance, which equals to about 264-μF Co effective value, which is much higher than the 106 μF upper limit without Cff.
This example has been validated on the TPS62933EVM. C3216X5R1V226M160AC (22 μF) and CGA5L1X7R1H106K160AC (10 μF) are selected as Co, the effective value of C3216X5R1V226M160AC is about 13.2 μF when biased at 5 V, the effective value of CGA5L1X7R1H106K160AC is about 9.4 μF.
Since 20 × parallel capacitors are used, the ESR of output capacitors can be ignored. With Equation 17 and Equation 18, the range of Cff as Cff > 425 pF, is calculated. So, 470 pF Cff is selected for the application.
Figure 5-1 shows the bode plot test results with added 470 pF Cff. The phase margin is boosted to 83.464 degrees, which validates the effectiveness of the proposed method. See more validation results in Section A.