SLUAAH0 February 2022 UCC14130-Q1 , UCC14131-Q1 , UCC14140-Q1 , UCC14141-Q1 , UCC14240-Q1 , UCC14241-Q1 , UCC14340-Q1 , UCC14341-Q1 , UCC15240-Q1 , UCC15241-Q1
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The UCC14240-Q1 is a high-efficiency, low-emissions, 3-kVRMS isolated DC-DC converter module capable of delivering up to 1.5-W of power. The UCC14240-Q1 integrates the control, power switches and transformer into a wide-body, 16-pin SOIC package. This allows systems to reduce size and cost by removing the need for separate isolated power supplies. The UCC14240-Q1 delivers class-leading efficiency in bias supply, power conversion from the primary to the secondary side while removing the need for bulky external transformers or power modules commonly used in existing designs.
This higher level of integration requires fewer components and less printed circuit board (PCB) area as well as significantly reduced height profile compared to discrete and modular power isolation techniques used in the field today. The UCC14240-Q1 operates from an input voltage range of 21 V<VIN<27 V. EV and HEV battery management systems (BMS) and traction inverters use voltage regulators to manage the wide voltage range (typically: 6 V<12 V<40 V) of the 12-V battery. Similarly, an isolated, redundant regulator is sometimes applied to the high-voltage (HV) battery stack with outputs made available to the low-voltage (LV) primary. Either or both of these regulators can easily be programmed to provide 24-V to the UCC14240-Q1 input. The UCC14240-Q1 is then used to convert 24 V from the LV primary to an isolated DC voltage of 18 V<VDD-VEE<25 V on the HV secondary.
Isolated gate driver ICs used in EV and HEV, HV applications are often driving insulated gate bipolar transistors (IGBTs) or silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs). IGBTs and SiC MOSFETs can switch between zero and a positive voltage (VDD) but more typically require VDD during turn-on and a negative voltage (VEE) during turn-off. The UCC14240-Q1 is easily configurable between single output VDD bias voltage or dual output positive VDD and negative VEE bias voltage.
PIN | TYPE (1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
GNDP | 1, 2, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 | G | Primary-side ground connection for VIN. Place several vias to copper pours for thermal relief. See Section 12. |
/PG | 3 | O |
Active low powergood open-drain output pin. /PG pulled low when (UVLO ≤ VIN ≤ OVLO); (UVP1 ≤ (VDD – VEE) ≤ OVP1); (UVP2 ≤ (COM – VEE) ≤ OVP2); TJ_Primary ≤ TSHUT_primary; and TJ_secondary ≤ TSHUT_secondary |
ENA | 4 | I | Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device functionality. 5.5-V recommended maximum. |
VIN | 6, 7 | P | Primary input voltage. Connect a 2.2-µF ceramic capacitor from VIN to GNDP. Connect a 0.1-µF high-frequency bypass ceramic capacitor close the IC pins. |
VEE | 19, 20, 21, 22, 23, 24, 25,26, 27, 30,31, 36 | G |
Secondary-side reference connection for VDD and COM. The VEE pins are used for the high current return paths. |
VDD | 28, 29 | P | Secondary-side isolated output voltage from transformer. Connect a 2.2-µF and a parallel 0.1-µF ceramic capacitor from VDD to VEE. The 0.1-µF ceramic capacitor is the high frequency bypass and must be next to the IC pins. |
RLIM | 32 | P | Secondary-side second isolated output voltage resistor to limit the source current from VDD to COM node, and the sink current from COM to VEE. Connect a resistor from RLIM to COM to regulate the (COM – VEE) voltage. See Section 8.1 for more detail. |
FBVEE | 33 | I | Feedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage. Connect a resistor divider from COM to VEE so that the midpoint is connected to FBVEE, and the equivalent FBVEE voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVEE and VEEA IC pins on the top layer or back layer connected with vias. |
FBVDD | 34 | I | Feedback (VDD – VEE) output voltage sense pin and to adjust the output (VDD – VEE) voltage. Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and the equivalent FBVDD voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVDD and VEEA IC pins on the top layer or back layer connected with vias. |
VEEA | 35 | G | Secondary-side analog sense reference connection for the noise sensitive analog feedback inputs, FBVDD and FBVEE. Connect the low-side feedback resistors and high frequency decoupling filter capacitor close to the VEEA pin and respective feedback pin FBVDD or FBVEE. Connect to secondary-side gate drive lowest voltage reference, VEE. Use a single point connection and place the high frequency decoupling ceramic capacitor close to the VEEA pin. See Section 12. |
The traction inverter is part of the electric drive that controls the electric motor responsible for propulsion of the vehicle. This is a key part of the HEV, EV electrical system used to convert DC power from the HV battery stack to three-phase, AC power used to drive the two or more electric motors.
The galvanic isolation between the LV primary and HV secondary is shown by the red dashed line in the traction inverter block diagram shown in Figure 2-1. Motor diagnostics, voltage and current sensing and a HV DC-DC power converter are a few examples shown where digital signals and power are passing from the HV battery and motor side to the LV battery side. The focus of this application report is on the isolated bias supply, which converts a DC voltage from the LV battery side to the HV battery side used to bias the HS and LS drivers in the power stage.
Traction inverters have unique gate drive bias architectures based on required levels of safety, isolation, fault detection, reliability and load. The load seen by the gate drivers consists of SiC MOSFETs or IGBTs arranged in a half-bridge, three-phase configuration. Since there are three phases to consider, this means there are three half-bridge arrangements that must be properly isolated and biased. SiC and IGBT switches are favored over Si MOSFETs because of their superior HV, dynamic switching characteristics, current handling capability and high temperature rating.
This section will consider the impact of the following, from an isolated bias supply point of view: gate drive bias architectures, IGBT vs SiC requirements, determining required bias supply power, input voltage requirements and output voltage regulation requirements.