SLUAAH0 February   2022 UCC14130-Q1 , UCC14131-Q1 , UCC14140-Q1 , UCC14141-Q1 , UCC14240-Q1 , UCC14241-Q1 , UCC14340-Q1 , UCC14341-Q1 , UCC15240-Q1 , UCC15241-Q1

 

  1.   Trademarks
  2. 1 Introduction
    1. 1.1 Pin Configuration and Functions
  3. 2 Three-Phase Traction Inverter
  4. 3 Gate Drive Bias Requirements
    1. 3.1 Gate Drive Bias Architectures
    2. 3.2 IGBT vs. SiC
    3. 3.3 Determining Required Bias Supply Power
    4. 3.4 Input Voltage Requirements
    5. 3.5 Output Voltage Requirements
  5. 4 Single Positive Isolated Output Voltage
  6. 5 Dual Positive and Negative Output Voltages
  7. 6 Dual Positive Output Voltages
  8. 7 Capacitor Selection
  9. 8 RLIM Current Limit Resistor
    1. 8.1 RLIM Functional Description
    2. 8.2 RLIM Dual Output Configuration
      1. 8.2.1 CVEE Above Nominal Value CVDD Below Nominal Value
      2. 8.2.2 CVEE Below Nominal Value CVDD Above Nominal Value
      3. 8.2.3 Gate Driver Quiescent Current: IQ_VEE > IQ_VDD
      4. 8.2.4 Gate Driver Quiescent Current: IQ_VEE < IQ_VDD
      5. 8.2.5 CVEE Above Nominal Value CVDD Below Nominal Value: IQ_VEE > IQ_VDD
      6. 8.2.6 CVEE Below Nominal Value CVDD Above Nominal Value: IQ_VEE < IQ_VDD
    3. 8.3 RLIM Single Output Configuration
  10. 9 UCC14240-Q1 Excel Design Calculator Tool
  11. 10Thermal Considerations
    1. 10.1 Thermal Resistance
    2. 10.2 Junction-to-Top Thermal Characterization Parameter
    3. 10.3 Thermal Measurement and TJ Calculation Example
  12. 11Enable (ENA) and Power Good (/PG)
  13. 12PCB Layout Considerations
  14. 13Reference Design Example
  15. 14Summary
  16. 15References

8.2.6 CVEE Below Nominal Value CVDD Above Nominal Value: IQ_VEE < IQ_VDD

The case shown in Figure 8-6 is the combination of case 2 (Figure 8-2) and case 4 (Figure 8-4) where the RLIM regulator is sinking current from the gate driver COM pin. This is the worst case where the voltage across CVEE (COM-VEE) drifts higher resulting in ILIM sinking additional compensating current through RLIM to restore equal capacitor charge balance.



Figure 8-6 Case 2 and Case 4: CVEE Lower, CVDD Higher, IQ_VEE < IQ_VDD

The additional compensated charge, ΔQC_DN, as a result of the worst case expected capacitor variation ΔCVDD and ΔCVEE is given by Equation 32 which is Equation 24 repeated here for completeness.

Equation 32. ∆QC_DN=QG×CVDD×(1-∆CVDD)CVDD×1-∆CVDD+CVEE×1-∆CVEE-CVDDCVDD+CVEE

RLIM is calculated from Equation 33 and the power dissipated is given from Equation 34 where the total ILIM now consists of ΔQC_DN derived from the total capacitor variation and IQ variation for the case that IQ_VEE < IQ_VDD.

Equation 33. RLIM=COM-VEEILIM-RINT_DN=COM-VEE∆QC_DN×FSW+IQ_VDD-IQ_VEE-RINT_DN
Equation 34. PRLIM=ILIM2×RLIM=∆QC_DN×FSW+IQ_VDD-IQ_VEE2×RLIM

If the selected value of RLIM is too low, the peak IDD current can increase causing oscillations on VDD which can result in the UCC14240-Q1 entering an overload, shut-down condition. Conversely, if the value of RLIM is too high, the charge rate of CVDD and especially CVEE will be slow due to a higher RC time constant. The result will appear as VDD-VEE reaching regulation much sooner compared to COM-VEE, resulting in VDD-COM voltage overshoot during start-up. Selecting CVDD and CVEE excessively larger than the results of Equation 19 and Equation 20 will exasperate the problem of slow COM-VEE response and VDD-COM voltage overshoot. Careful selection of CVDD, CVEE and RLIM is important for optimizing the UCC14240-Q1 start-up and transient performance. Determining UCC14240-Q1 required component values is greatly simplified by using the Excel UCC14240-Q1 Design Calculator Tool, described in the Section 9 section.