SLUAAH0 February   2022 UCC14130-Q1 , UCC14131-Q1 , UCC14140-Q1 , UCC14141-Q1 , UCC14240-Q1 , UCC14241-Q1 , UCC14340-Q1 , UCC14341-Q1 , UCC15240-Q1 , UCC15241-Q1

 

  1.   Trademarks
  2. Introduction
    1. 1.1 Pin Configuration and Functions
  3. Three-Phase Traction Inverter
  4. Gate Drive Bias Requirements
    1. 3.1 Gate Drive Bias Architectures
    2. 3.2 IGBT vs. SiC
    3. 3.3 Determining Required Bias Supply Power
    4. 3.4 Input Voltage Requirements
    5. 3.5 Output Voltage Requirements
  5. Single Positive Isolated Output Voltage
  6. Dual Positive and Negative Output Voltages
  7. Dual Positive Output Voltages
  8. Capacitor Selection
  9. RLIM Current Limit Resistor
    1. 8.1 RLIM Functional Description
    2. 8.2 RLIM Dual Output Configuration
      1. 8.2.1 CVEE Above Nominal Value CVDD Below Nominal Value
      2. 8.2.2 CVEE Below Nominal Value CVDD Above Nominal Value
      3. 8.2.3 Gate Driver Quiescent Current: IQ_VEE > IQ_VDD
      4. 8.2.4 Gate Driver Quiescent Current: IQ_VEE < IQ_VDD
      5. 8.2.5 CVEE Above Nominal Value CVDD Below Nominal Value: IQ_VEE > IQ_VDD
      6. 8.2.6 CVEE Below Nominal Value CVDD Above Nominal Value: IQ_VEE < IQ_VDD
    3. 8.3 RLIM Single Output Configuration
  10. UCC14240-Q1 Excel Design Calculator Tool
  11. 10Thermal Considerations
    1. 10.1 Thermal Resistance
    2. 10.2 Junction-to-Top Thermal Characterization Parameter
    3. 10.3 Thermal Measurement and TJ Calculation Example
  12. 11Enable (ENA) and Power Good (/PG)
  13. 12PCB Layout Considerations
  14. 13Reference Design Example
  15. 14Summary
  16. 15References

CVEE Above Nominal Value CVDD Below Nominal Value: IQ_VEE > IQ_VDD

Finally, consider the ILIM contribution for the combined effect of CVDD to CVEE capacitor value mismatch and gate driver IQ variation. The case shown in Figure 8-5 is the combination of case 1 (Figure 8-1) and case 3 (Figure 8-3) where the RLIM regulator is sourcing current into the gate driver COM pin. This is the worst case where the voltage across CVEE (COM-VEE) drifts lower resulting in ILIM sourcing additional compensating current through RLIM to restore equal capacitor charge balance.



Figure 8-5 Case 1 and Case 3: CVEE Higher, CVDD Lower, IQ_VEE > IQ_VDD

The additional compensated charge, ΔQC_UP, as a result of the worst case expected capacitor variation ΔCVDD and ΔCVEE is given by Equation 29 which is Equation 21 repeated here for completeness.

Equation 29. QC_UP=QG×CVEE×(1-CVEE)CVDD×1-CVDD+CVEE×1-CVEE-CVEECVDD+CVEE

RLIM is calculated from Equation 30 and the power dissipated is given from Equation 31 where the total ILIM now consists of ΔQC_UP derived from the total capacitor variation and IQ variation for the case that IQ_VEE > IQ_VDD.

Equation 30. RLIM=VDD-COMILIM-RINT_UP=VDD-COMQC_UP×FSW+IQ_VEE-IQ_VDD-RINT_UP
Equation 31. PRLIM=ILIM2×RLIM=QC_UP×FSW+IQ_VEE-IQ_VDD2×RLIM