SLUAAH0 February 2022 UCC14130-Q1 , UCC14131-Q1 , UCC14140-Q1 , UCC14141-Q1 , UCC14240-Q1 , UCC14241-Q1 , UCC14340-Q1 , UCC14341-Q1 , UCC15240-Q1 , UCC15241-Q1
Finally, consider the ILIM contribution for the combined effect of CVDD to CVEE capacitor value mismatch and gate driver IQ variation. The case shown in Figure 8-5 is the combination of case 1 (Figure 8-1) and case 3 (Figure 8-3) where the RLIM regulator is sourcing current into the gate driver COM pin. This is the worst case where the voltage across CVEE (COM-VEE) drifts lower resulting in ILIM sourcing additional compensating current through RLIM to restore equal capacitor charge balance.
The additional compensated charge, ΔQC_UP, as a result of the worst case expected capacitor variation ΔCVDD and ΔCVEE is given by Equation 29 which is Equation 21 repeated here for completeness.
RLIM is calculated from Equation 30 and the power dissipated is given from Equation 31 where the total ILIM now consists of ΔQC_UP derived from the total capacitor variation and IQ variation for the case that IQ_VEE > IQ_VDD.