SLUAAH0 February 2022 UCC14130-Q1 , UCC14131-Q1 , UCC14140-Q1 , UCC14141-Q1 , UCC14240-Q1 , UCC14241-Q1 , UCC14340-Q1 , UCC14341-Q1 , UCC15240-Q1 , UCC15241-Q1
Within the HS Driver and LS Driver power stage blocks of Figure 2-1 exists one of three unique configurations for distributing the bias supply voltage to each of the isolated gate drivers. Gate drive bias architectures are typically classified into three main types: centralized, distributed and semi-distributed. Hybrid examples also exist and tend to be based on one or more of the three types shown in Figure 3-1.
The centralized architecture achieves isolation through a single transformer used to bias all six drivers. Because the transformer must be rated for the full bias power and achieve primary to secondary isolation between multiple windings, this results in the largest size transformer among the three architectures. Furthermore, if any single winding fails, the transformer fails, losing bias voltage to all three inverter phases. This is the least preferred option from a size, weight, and fault isolation point of view.
At the other end of the spectrum, we see the distributed architecture with six individual bias supplies and six isolation transformers. For fault detection and reliability, distributed architectures are the best approach but are often discounted because of the higher number of components required. The benefit is that a bias failure at any single gate driver can be detected and corrective action assigned, allowing the EV to remain operating with a reduction in traction inverter performance. Here, the total required bias power is divided between each of the six converters. While the power delivered to each gate driver is reduced by six, a proportional reduction in transformer size cannot be fully realized due to the winding spacing and separation required to meet isolation standards. This is a limitation of traditional wire wound transformers the UCC14240-Q1 has overcome. A 3-kVRMS isolation transformer, control and power stage capable of 1.5-W bias power rated to 105°C integrated in a 3.55-mm height, SOIC package make the UCC14240-Q1 perfectly suited for distributed bias architectures.
Semi-distributed architectures can also take advantage of UCC14240-Q1 to bias GD1, GD3 and GD5 when the required power for each is less than 1.5 W. For the low-side bias of GD2, GD4 and GD6, when the total required power exceeds 1.5 W, the UCC25800-Q1 Ultra-low EMI Transformer Driver is a perfect companion to the 3x UCC14240-Q1 for building a high-performance, semi-distributed, isolated gate drive bias system.