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Device | UCC28056A | UCC28056B | UCC28056C |
---|---|---|---|
Where Used | PFC Output > 400 V | Application With Minimal Audible Noise | General Purpose |
Overvoltage Protection Threshold | 108% VOUT | 110% VOUT | 110% VOUT |
Second Tier Overvoltage Protection Enabled | ✓ | ✓ | |
Burst Mode Threshold | < 15% Load | < 15% Load | < 10% Load |
The UCC28056 families integrate the Zero Current Detection (ZCD) and the Current Sense (CS) feature together at the ZCD/CS pin, to reduce the package size. This makes the devices cost-competitive in of the smallest packages available. The device layout is designed for both precise detection of drain-to-source voltage and OCP signal sampling. The UCC28056A, UCC28056B, and UCC28056C have improved the noise immunity on the ZCD pin making the controller more robust and less sensitive to noise from downstream.
Table 1-1 shows the key differences of each version. The UCC28056A removes the OVP2 feature. Use this device in applications with wider input voltage range and high output voltage. TI also recommends using the device in applications that are not allowed any restart event during surge or lighting test.
The UCC28056C has a lower burst mode threshold compared with the UCC28056A and UCC28056B. Use the UCC28056C in applications that need lower burst mode power.
The minimum frequency for UCC28056C is around 18 kHz to 20 kHz, and UCC28056A, UCC28056B minimum frequency can be higher than 20 kHz. For some applications that detect the audible noise through audible noise test equipment and scan the frequency from 20 Hz to 20 kHz, select the UCC28056A or UCC28056B version.
For more information about the differences of each version, see the UCC28056 Selection Guide application brief.
Review the UCC28056 schematic using the simplified application in Figure 2-1 and check each pin of the controller.
The VOSNS pin voltage is applied to the inverting input of an internal transconductance error amplifier. The output voltage regulation set point (VOutReg) is determined by the external resistor divider network connecting the output voltage to the VOSNS pin. To ensure that the VOSNS pin bias current degrades output voltage regulation by less than 1%, the upper voltage divider resistor value must be less than 39 MΩ. Although it is possible to increase the divider resistance to reduce the standby power, there is some impact on the output voltage regulation accuracy across parts and temperature, so design the total voltage divider resistance to be around 10 MΩ. The capacitance on the VOSNS pin helps to filter the switching noise and use SMD capacitance with a value of less than 3.3 nF. A higher value may increase the PFC output voltage loop response time.