SLUAAH3 October   2021 UCC28056

 

  1.   Trademarks
  2. 1How to Select the Correct Devices Version of UCC28056 Families?
  3. 2How to Complete the Schematic Review of the UCC28056?
    1. 2.1 VOSNS Pin
    2. 2.2 ZCD/CS Pin
    3. 2.3 DRV Pin
    4. 2.4 GND Pin
    5. 2.5 VCC Pin
    6. 2.6 COMP Pin
  4. 3How to Test and Confirm the UCC28056 Working Mode?
    1. 3.1 How to Capture the ZCD/CS Waveform?
    2. 3.2 How to Evaluate UCC28056 Normal Operation Mode Waveform?
  5. 4Protections and how to Identify Them?
    1. 4.1 OVP1
    2. 4.2 OVP2
    3. 4.3 OCP1
    4. 4.4 OCP2
  6. 5Application Debug Frequently Asked Questions (FAQs).
    1. 5.1  How is the UCC28056 GND Pin Connected?
    2. 5.2  There is CCM Inductor Current During Start-Up, is This a Normal Phenomenon?
    3. 5.3  How to Fine-Tune the RC Parameter on the ZCD/CS Pin?
    4. 5.4  Is it Possible to Increase the High Voltage Cap Value on the ZCD Cap Divider?
    5. 5.5  How to Separate the TONMAX Limit or OCP Protection When the PFC Output Voltage Cannot Follow the Regulated Voltage?
    6. 5.6  Does UCC28056 Support DC Input Application?
    7. 5.7  How Does RDG Change the Delay Time for Valley Switching Detection of the MOSFET?
    8. 5.8  Can UCC28056 Meet Harmonic Performance?
    9. 5.9  Does UCC28056 Have Soft Start?
    10. 5.10 Does the UCC28056 Support Auxiliary-Winding PFC Inductor Input on the ZCD Pin?
  7. 6References

2.1 VOSNS Pin

The VOSNS pin voltage is applied to the inverting input of an internal transconductance error amplifier. The output voltage regulation set point (VOutReg) is determined by the external resistor divider network connecting the output voltage to the VOSNS pin. To ensure that the VOSNS pin bias current degrades output voltage regulation by less than 1%, the upper voltage divider resistor value must be less than 39 MΩ. Although it is possible to increase the divider resistance to reduce the standby power, there is some impact on the output voltage regulation accuracy across parts and temperature, so design the total voltage divider resistance to be around 10 MΩ. The capacitance on the VOSNS pin helps to filter the switching noise and use SMD capacitance with a value of less than 3.3 nF. A higher value may increase the PFC output voltage loop response time.