UCC25640x has a minimum detectable slew rate of 100 mV/ns. As soon as the high side gate (HO) is turned off, the low side gate (LO) is be turned on after the slew rate has been detected. If the slew rate detection is missed, the dead time depends on the resonant current polarity (Section 1.19). Figure 1-10 shows a way of extracting slew rate information during the dead time [10]. In this simulation Infineon IPW6075CP MOSFET is used as an example. Figure 1-11 shows the switch node voltage transition when a current of 0.7 A is being pulled out from switch node. Here we can observe that switch node voltage has different slew rates during the transition which is due to non linear capacitance (Figure 1-15) seen at the switch node. This non linear capacitance is combination of Coss of the both upper (voltage changing from 0 V to 390 V) and lower (voltage changing from 390 V to 0 V) MOSFETs as shown in Figure 1-13 and Figure 1-14. The Coss graphs of each MOSFETs are extracted using the SIMetrix simulation. The extractions are shown in Figure 1-12.

The following methods can be followed to improve the slew rate detection:

1. Increase the MOSFET turn off speed: Most designs include a diode in the HO/LO gate drive paths to allow for independent turn on and turn off speed. Such a circuit is recommended to increase the turn off speed of the gate drive.
2. Using MOSFETs with lower output capacitance (Coss): The lower Coss allow for a faster switch node slew rate.
3. Using a higher burst mode setting: A higher burst mode setting have larger magnetizing current amplitude which help with achieving the dV/dt criteria (Increasing the burst threshold make the LLC burst with slightly more power within the burst packet and the resonant current amplitude can be higher.
4. Reducing any snubber capacitance on the switch node
5. Reducing the magnetizing inductance of the transformer to increase the magnetizing current at light load.