Figure 3-1 shows the logic of OOB behavior when the output voltage is larger than OOB threshold (108%) but lower than OV threshold (125%). As the output voltage doesn't reach to OV threshold, device internal OV signal is kept low as well as OV_Latch signal.

When the output voltage is higher than 108% of target output value, the OOB_comparator outputs high, the OOB_Output signal is triggered which turns on low-side FET beyond zero inductor current to discharge output until reaches to NOC (if heavy external force) or output lower than target (if light over-voltage, for example load transient), then low-side FET is turned off and high-side FET is turned on. After maximum 16-cycle NOC triggered, OOB_Output signal will be ended.

The OOB_Output signal can be reset by OV signal or output falls below target (normal PWM control) or EN enabled.

Figure 3-2 and Figure 3-3 show the bench test waveforms for TPS56C230, test conditions are 12Vin, 1.2Vout, Eco-Mode, force external 1.4V to Vout. When output is higher than 108% of target, 2 cycles of NOC are triggered and output is discharged. During the third cycle of low-side FET on, output voltage is discharged lower than target, so low-side FET is off and high-side FET is on without triggering NOC. The bench behaviors match with Figure 3-1 logic diagram.