2 MOSFET Selection for TPS53211 Synchronous BUCK controller

Efficiency of energy conversion, useful output power divided by total input power, is one of the fundamental performance metrics of a voltage regulator. With BUCK regulator controllers like the TPS53211, selection of the power stage, especially the power MOSFETS, is critical to optimizing the performance of the converter.

Maximizing efficiency is most effectively seen as minimizing loss factors, such as RDSON conduction losses, switch transition losses and gate drive losses for the external power FETs. Since larger MOSFETs with lower RDSON typically have higher gate charge and thus gate drive and switching losses, minimizing loss and maximizing efficiency is best considered as a balance between these loss factors. Minimum loss and thus maximum efficiency occurs when gate-charge driven losses, such as switch transition and gate drive losses, and RDSON driven conduction losses are equal. Further reducing one increases the other more than the prior is reduced.

One method for selecting MOSFETs with the optimum RDSON versus Gate Charge ratio is called the J/K method. In this method, J represents the MOSFET gate-charge related switching and gate drive losses while K represents the RDSON conduction related losses.

Control (High-side) MOSFET

Rectifying (Low-side) MOSFET

With the optimum MOSFET at the operating condition of V_IN to V_OUT @ I_OUT having the R_DS(ON) / Q_sw = J / K.

For more about optimized MOSFET selection and balancing gate-charge and conduction losses using the J/K Method see – The J/K Method: A Technique for Selecting the Optimal MOSFET.

1. Limit total gate drive current to less than 50 mA to avoid overloading the internal VCCDR regulator.
   1. When VCCDR is not powered by an external supply, VCCDR is powered by an internal 6.5-V linear regulator powered from VCC. The VCCDR regulator’s current limit can be as low as 50 mA, so the total gate charge of all high-side and low-side MOSFETs times the switching frequency should be less than 50 mA. For example, with a 500 kHz switching frequency, the combined gate charge of all MOSFETs should be less than 100 nC.
2. Limit Low-side FET gate charge to less than 55 nC
   1. During the turn-off of the low-side MOSFET, the low-side FET gate charge is discharged through LGATE to the GND pin. The high current and duration of this discharge can disrupt the GND pin when the total low-side FET gate charge is greater than 55 nC
   2. If low-side MOSFETs with total gate charge greater than 55 nC must be used, 1-Ω-2.2-Ω series resistors need to be added between LGATE and the MOSEFT gate pins to limit the discharge current.
3. If multiple MOSFETs are used in parallel, each needs to use its own series gate resistor
   1. While multiple MOSFETs are unusual for the TPS53211 controller, given the limited gate-drive current and low-side FET gate charge, if multiple MOSFETs are used, each MOSFET have a separate gate resistor.
   2. Since each MOSFET will have a slightly different gate threshold voltage, using separate resistors allows parallel MOSFETs maintain separate gate-source voltages during their switch transition, balancing their switching losses.

Within these limitations, the TPS53211 can drive a wide range of Power MOSFETs and meet the efficiency requirements of most applications. To reduce switching and gate-driver losses at currents below critical conduction mode, the TPS53211 includes an “auto-skip” function that switches to discontinuous conduction mode with diode emulation of the low-side FET and reduced the switching frequency with Pulse Frequency Modulation when the load current is less than ½ of the continuous conduction peak to peak inductor ripple current.