SLUAAN8 January 2023 BQ40Z50
Table 2-1 shows the changes from the BQ40Z50-R4 device to the BQ40Z50-R5 device.
| Change Description | BQ40Z50-R5 | BQ40Z50-R4 | Comments |
|---|---|---|---|
| Enabled CHG FET to turn off in SLEEP mode, even if [PRES] = 1 | Expanded feature | FET Options[SLEEPCHG] now applies to in-system SLEEP mode. | Enables the option to reduce power consumption in SLEEP mode for integrated battery packs. |
| Updated the voltage based cell balancing algorithm when the device is in REST mode | New feature | Feature does not exist. | Enables voltage based cell balancing operation to continue after the device enters REST mode. |
Added voltage or RSOC Option for C-Rate transitions in Advanced Charge Algorithm | New feature | Feature does not exist. | Enables a C-Rate stepdown to be based on voltage or RSOC so an aged battery with lower voltage at the same RSOC level can step down the C-rate earlier. |
Changed the Turbo Cfg C-rate entry unit from 0.1°C to 0.01°C | Modified feature | Less resolution with TURBO mode parameters | Enables customers to enter a decimal c-rate value during TURBO mode to reduce power loss due to rounded down c-rate. |
Added cycle count stamp to Black Box event under Lifetimes DF | New feature | Feature does not exist. | Helps to reduce system debug effort when debugging safety or PF events. |
Added a programmable temp range for Lifetime RSOC-Temp recording | New feature | Feature does not exist. | Enables customers to record RSOC with increase granularity at a higher temperature, because temperature effects are exponential at a higher temperature. |
Added an unseal key when writing to Manufacturing Info Block C during SEAL mode | New feature | Feature does not exist. | Provides additional data override protection for Manufacturing Info Block C. |
Added a threshold to temperature delta between cells | New feature | Feature does not exist. | Prevents a serious temperature gap between adjacent cells, which can lead to a cell imbalance and other serious issues. |
Added the EVLTM/EVMTM/EVHTM time tracking and five cell voltage stepdowns | New feature | Feature does not exist. | To better control CV due to cell aging, the ERETM function is expanded to provide more voltage steps down due to increasing temperature. |
Added [SLOW CRATE] option to slow down current change rate by 5 times. | Modified feature | Feature does not exist. | Slows down the current transistion by multiplying the Current Rate by 5, effectively making the current step size smaller, and taking 5 times as many 1-second steps to transistion to the target ChargingCurrent(). |
Added Low RSOC time-based shutdown | New feature | Feature does not exist. | Allows automatic Time-Based Shutdown after a low RSOC condition is detected. |
Added STORAGE Mode activation feature | New feature | Feature does not exist. | Addtional low power option while in SLEEP which disables the CHG and DSG FETs. Enables device wake up by pressing a button to pull SMBus lines high. |
Added functionality to prevent flash wearout when writing to MAC 0x00B0 and 0x00B2 commands | New Feature | Feature does not exist. | The feature is to prevent over-usage of the MAC 0x00B0 and 0x00B2 commands from causing severe data flash wear by introducing the Sealed Write.Hold Off and the Sealed Write.Lockout parameters. The Sealed Write.Hold Off parameter sets the delay time before new values are written to the data flash, and the Sealed Write.Lockout parameter sets the period of lockout time before a new value can again be written to the data flash after the previous write. |
Enabled the ChargingCurrent() to be lower than Pre-Charging:Current if desired | Modified feature | Prevented the ChargingCurrent() from going to a JEITA setting which is < Pre-Charging:Current | This feature helps to prevent the charging degradation algorithm from reducing and causing the ChargingCurrent() to fall below Pre-Charging:Current. The corrected implementation now allows the ChargingCurrent() to take on a JEITA setting that is < Pre-Charging:Current even if the charge degradation iss enabled. |
Fixed LStatus and Balance Status registers in the BQStudio configuration file to display properly on the main Bit Registers page | Modified feature | Registers are mapped as integers instead of hex. | Changed mapping to hex: LStatus and Balance Status were mapped as integers instead of hex in the previous releases, which led to the incorrect bits labeled as active in the BQStudio register display. BQ40Z50-R5 corrects this issue. |