2 Problems with a Synchronous Rectification Strategy

To reduce the number of sensors, a synchronous rectification strategy based on secondary-side current sampling combined with a primary-side drive signal is proposed. Taking the forward operation of the CLLLC resonant converter as an example, assume that the converter operates in boost mode (f_s < f_r), as shown in Figure 2-1.

The synchronous rectifier switches Q₅ and Q₈ are turned on at the same time as Q₂ and Q₃, and the switch turns off when i_Lr2 is detected at 0. While these actions are not a problem in this mode as shown, problems can occur if the converter works in over-resonant mode (f_s > f_r).

As shown in the top-right graph of Figure 2-2, in the dead time from t₁ to t₃, i_Lr1 = i_Lm at the t₂ moment, causing the secondary current to begin to commutate, and the t₃ moment Q₂/Q₃ is now on. At this time there is no problem with turning on the secondary-side rectifier switch, but such situations do exist, as shown in the bottom-right graph of Figure 2-2. The dead time is relatively short, as until the end of the dead zone, i_Lr1 is still greater than i_Lm. At this time Q₂/Q₃ is turned on (t₂), and i_Lr1 is still higher than i_Lm until equal to i_Lm (t3). At this time, the secondary side begins to commutate if the original logic is still used. When the synchronous rectifier switch is turned on together with Q₂/Q₃, the switch is turned on in advance, causing the current waveform to oscillate.

Figure 2-1 Current Waveforms When f_s < f_r

Figure 2-2 Current Waveforms When f_s > f_r

So, under situations like this, providing an acceptable delay is necessary to make sure that SR is not turned on in advance.