In addition to R_FSEL used to select the internal PWM oscillator frequency, there is a single resistor in series between the clock generator and capacitor, referred to as R1 in Figure 2-1. A requirement is to use a 1% tolerance resistor or better.

The acceptable values for R1 depend on the chosen clock signal amplitude and switching frequency. At lower switching frequencies, there is less voltage drop across this circuit, resulting in a higher voltage applied to the SYNC/FSEL pin, but still lower than the clock signal amplitude. In this case, a higher value for R1 can be used as long as the SYNC/FSEL pin receives at least 1.8V. When a high switching frequency is selected, there is a greater amount of voltage drop across this circuit, thus a lower R1 value must be used for 1.8V to reach the SYNC/FSEL pin. The results of all the tested R1 and switching frequency values are tabulated in Table 3-1.

When using a 3.3V clock signal, the recommended value for R1 is 1.1kΩ, as this keeps the voltage applied to the SYNC/FSEL pin above the necessary 1.8V threshold while keeping the negative voltage element above -300 mV across all selectable switching frequencies.