A minimum voltage of 1.8V is needed to be applied to the SYNC/FSEL pin of the TPS543620 to enable clock synchronization. The clock signal frequency needs to also be within ±20% of the frequency set by R_FSEL. The chosen switching frequency setting also has an effect on the voltage applied to the SYNC/FSEL pin. At lower switching frequencies, there is less voltage drop across this circuit, resulting in a higher voltage applied to the SYNC/FSEL pin. Common clock signal amplitudes include 1.8V, 2.5V, 3.3V, and 4.5V.

A clock signal of at least 3.3V is recommended to reach the minimum high-level input voltage of 1.8V across all possible selectable switching frequencies of the device, assuming that a 1.1kΩ R1 is used. Using a clock signal greater than 3.3V is possible and can allow for greater possible R1 values. Using a lower clock voltage than 3.3V is also possible, but there is a limitation to the switching frequency options possible and a lower R1 value can be needed to verify at least 1.8V is applied to the SYNC/FSEL pin.