SLUS157Q December 1999 – October 2019 UCC1895 , UCC2895 , UCC3895
PRODUCTION DATA.
The input voltage in this design is 390 VDC, which is generally fed by the output of a PFC boost pre-regulator. The input capacitance is generally selected based on holdup and ripple requirements.
NOTE
The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP).
Calculate tank frequency:
Estimated delay time:
Effective duty cycle clamp (DCLAMP):
VDROP is the minimum input voltage where the converter can still maintain output regulation. The converter’s input voltage would only drop down this low during a brownout or line-drop condition if this converter was following a PFC pre-regulator.
CIN was calculated based on one line cycle of holdup:
Calculate high frequency input capacitor RMS current (ICINRMS).
To meet the input capacitance and RMS current requirements for this design a 330-µF capacitor was chosen from Panasonic part number EETHC2W331EA.
This capacitor has a high frequency (ESRCIN) of 150 mΩ, measured with an impedance analyzer at 200 kHz.
Estimate CIN power dissipation (PCIN):
Recalculate remaining power budget:
There is roughly 5.0 W left in the power budget left for the current sensing network, and biasing the control device and all resistors supporting the control device.