Careful layout of the printed board is a necessity for high-frequency power supplies. As the device-switching speeds and operating frequencies increase, the layout of the converter becomes increasingly important.

This 8-pin device has only a single ground for the logic and power connections. This forces the gate-drive current pulses to flow through the same ground that the control circuit uses for reference. Thus, the interconnect inductance must be minimized as much as possible. One implication is to place the device (gate driver) circuitry close to the MOSFET it is driving. This can conflict with the need for the error amplifier and the feedback path to be away from the noise generating components.

The single most critical item in a PWM controlled printed-circuit board layout is the placement of the timing capacitor. While both the supply and reference bypass capacitor locations are important, the timing capacitor placement is far more critical. Any noise spikes on the C_CT waveform due to lengthy printed circuit trace inductance or pick-up noise from being in proximity to high power switching noise causes a variety of operational problems. Dilemmas vary from incorrect operating frequency caused by pre-triggering the oscillator due to noise spikes to frequency jumping with varying duty cycles, also caused by noise spikes. The placement of the timing capacitor must be treated as the most important layout consideration. Keep PC traces as short as possible to minimize added series inductance.