SLUS495J August   2001  – December 2023 UCC29002 , UCC39002

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
    1.     Pin Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Differential Current-Sense Amplifier (CS+, CS−, CSO)
      2. 6.3.2 Load-Share Bus Driver Amplifier (CSO, LS)
      3. 6.3.3 Load-Share Bus Receiver Amplifier (LS)
      4. 6.3.4 Error Amplifier (EAO)
      5. 6.3.5 Adjust Amplifier Output (ADJ)
      6. 6.3.6 Enable Function (CS+, CS−)
      7. 6.3.7 Fault Protection on LS Bus
      8. 6.3.8 Start-Up and Adjust Logic
      9. 6.3.9 Bias Input and Bias_OK Circuit (VDD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Start-Up Mode
      2. 6.4.2 Normal Running Mode
      3. 6.4.3 Fault Mode
      4. 6.4.4 Disabled Mode
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Paralleling the Power Modules
    3. 7.3 Typical Application
      1. 7.3.1 Measuring the Voltage Loop of a Power Module
      2. 7.3.2 Detailed Design Procedure
        1. 7.3.2.1 The Shunt Resistor
        2. 7.3.2.2 The CSA Gain
        3. 7.3.2.3 Determining RADJ
        4. 7.3.2.4 Error Amplifier Compensation
      3. 7.3.3 Application Curve
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
      1. 8.1.1 Documentation Support
    2. 8.2 Related Links
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9Revision History
  11.   Mechanical, Packaging, and Orderable Information

7.3.2.4 Error Amplifier Compensation

The total load-share loop unity-gain crossover frequency, fCO, must be set at least one decade below the lowest measured crossover frequency of the paralleled modules previously measured, fCO(module) (see Figure 7-5). Compensation of the transconductance error amplifier is accomplished by connecting a compensation resistor, REAO, in series with a capacitor, CEAO, between EAO and GND. Use Equation 8 and Equation 13 to calculate the values of these components. CEAO is calculated first.

Equation 8. C E A O ≥ g M 2 π × f C O × 2 × A C S A × A V × A A D J × A P W R f C O

where

  • gM is the transconductance of the Error Amplifier, typically 14mS.
  • fCO is the targeted crossover frequency of the load-share loop, minimally fCO(module)/10, preferably even lower
  • ACSA is the DC gain of the Current-Sense Amplifier. (R15, R16 refer to Figure 7-1.)
  • AV is the maximum voltage gain.
  • AADJ is the gain associated with the Adjust amplifier.
  • |APWR(fCO)| is the measured gain of the power module at the targeted load-share crossover frequency, fCO, converted from dB to V/V.
Equation 9. A C S A = R 16 R 15
Equation 10. A V = R S H U N T R L O A D = I O U T ( m a x ) × R S H U N T V O U T
Equation 11. A A D J = R A D J ∥ R S E N S E 500   Ω = R A D J × R S E N S E R A D J + R S E N S E × 500   Ω
Equation 12. A P W R f C O = 10 G M O D U L E ( f C O ) 20

where

  • GMODULE(fCO) is the measured value of the gain (in dB) from Figure 7-5, at the targeted load-share crossover frequency.

After the value of the CEAO capacitor is determined, the REAO value is calculated to achieve the desired current-sharing loop response using Equation 13.

Equation 13. R E A O = 1 2 π × f C O × C E A O