SLUS720F February   2007  – June 2019 TPS40195

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Electrical Characteristics
    5. 7.5 Dissipation Ratings
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Enable Functionality
      2. 8.3.2  Voltage Reference
      3. 8.3.3  Oscillator and Synchronization
      4. 8.3.4  Undervoltage Lockout (UVLO)
      5. 8.3.5  Soft Start
      6. 8.3.6  Selecting the Short Circuit Threshold
      7. 8.3.7  5-V Regulator
      8. 8.3.8  Prebias Start-up
      9. 8.3.9  Drivers
      10. 8.3.10 Power Good
      11. 8.3.11 Thermal Shutdown
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application 1
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Inductor, LOUT
          2. 9.2.1.2.2 Output Capacitor, COUT
          3. 9.2.1.2.3 Input Capacitor, CIN
          4. 9.2.1.2.4 Switching MOSFET, QSW
          5. 9.2.1.2.5 Rectifier MOSFET, QSR
          6. 9.2.1.2.6 Component Selection for the TPS40195
            1. 9.2.1.2.6.1 Timing Resistor, RT
            2. 9.2.1.2.6.2 Setting UVLO
            3. 9.2.1.2.6.3 Setting the Soft-Start Time
            4. 9.2.1.2.6.4 Short-Circuit Protection, RILIM
            5. 9.2.1.2.6.5 Voltage Decoupling Capacitors, CBP, and CVDD
            6. 9.2.1.2.6.6 Boost Voltage, CBOOST and DBOOST (optional)
            7. 9.2.1.2.6.7 Closing the Feedback Loop RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2 AND CPZ1
          7. 9.2.1.2.7 Application Curve
      2. 9.2.2 Typical Application 2
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Typical Application 3
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Related Parts
    3. 11.3 Documentation Support
      1. 11.3.1 Related Documentation
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

9.2.1.2.4 Switching MOSFET, QSW

The following key parameters must be met by the selected MOSFET.

  • Drain-to-source voltage, VDS, must be able to withstand the input voltage plus spikes that may be on the switching node. For this design a VDS rating of between 25 V and 30 V is recommended.
    • Equation 17. TPS40195 q_iqsw_lus720.gif

    For this design IDD should be greater than 4.1 A

  • Gate source voltage, Vgs, must be able to withstand the gate voltage from the control device. For the TPS40195 this is 5 V.

Target efficiency for this design is 90%. Based on 1.8-V output and 10-A operating current this equates to a power loss in the module of 1.8 W. The design allocates this power budget equally between the two power FETS and the inductor The equations below are used to calculate the power loss, PQSW, in the switching MOSFET.

Equation 18. TPS40195 q_pgate_lus720.gif
Equation 19. TPS40195 q_pqsw_lus720.gif
Equation 20. TPS40195 q_pcon_lus720.gif
Equation 21. TPS40195 q_psw_lus720.gif

where

  • PCON is conduction losses
  • PSW is switching losses
  • PGATE is gate drive losses
  • Qgd is drain source charge or miller charge
  • Qgs1 is gate source post threshold charge
  • Ig is gate drive current
  • Qg(TOT) is total gate charge from 0 V to the gate voltage
  • Vg is gate voltage

Equation 22 and Equation 23 describe the preliminary values for RDS(on) and (Qgs1 + Qgd). Note output losses due to QOSS and gate losses have been ignored here. Once a MOSFET is selected these parameters can be added. The switching MOSFET for this design should have an RDS (on) of less than 20 mΩ . The sum of Qgd and Qgs1 should be approximately 14.8 nC. . The Vishay SI7860ADP was selected for this design. This device has an RDS(on) of 9  mΩ and a (Qgs1+Qgd) of 13 nC. The estimated conduction losses are 0.135 W and the switching losses are 0.297 W. This gives a total estimated power loss of 0.432 W versus 0.6 W for our initial boundary condition. Note this does not include gate losses of approximately 10 mW.