SLUS724F September   2006  – January 2022 BQ2022A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC
    6. 6.6 Switching Characteristics: AC
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 1024-Bit EPROM
      2. 7.3.2 EPROM Status Memory
      3. 7.3.3 Error Checking
      4. 7.3.4 Customizing the BQ2022A
      5. 7.3.5 Bus Termination
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1  Serial Communication
      2. 7.5.2  Initialization
      3. 7.5.3  ROM Commands
        1. 7.5.3.1 READ ROM Command
        2. 7.5.3.2 SKIP ROM Command
      4. 7.5.4  Memory/Status Function Commands
      5. 7.5.5  READ MEMORY Commands
        1. 7.5.5.1 READ MEMORY/Page CRC
        2. 7.5.5.2 READ MEMORY/Field CRC
      6. 7.5.6  WRITE MEMORY Command
      7. 7.5.7  READ STATUS Command
      8. 7.5.8  WRITE STATUS Command
      9. 7.5.9  PROGRAM PROFILE Byte
      10. 7.5.10 SDQ Signaling
      11. 7.5.11 RESET and PRESENCE PULSE
      12. 7.5.12 WRITE Bit
      13. 7.5.13 READ Bit
      14. 7.5.14 PROGRAM PULSE
      15. 7.5.15 IDLE
      16. 7.5.16 CRC Generation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming Circuit Example
        2. 8.2.2.2 SDQ Master Best Practices
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
      2. 11.2.2 Receiving Notification of Documentation Updates
    3. 11.3 Trademarks
    4. 11.4 Support Resources
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

7.5.10 SDQ Signaling

All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, or to begin the start frame for a bit read. Figure 7-9 shows the initialization timing, whereas Figure 7-10 and Figure 7-11 show that the host initiates each bit by driving the DATA bus low for the start period, tWSTRB / tRSTRB. After the bit is initiated, either the host continues controlling the bus during a WRITE, or the BQ2022A responds during a READ.